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MTS Process Integration Engineer, APTD at Micron Technology

Boise, Idaho, United States -

Full Time

Start Date

Immediate

Expiry Date

07 Apr, 26

Salary

0.0

Posted On

07 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Process Integration, Semiconductor Manufacturing, Fabrication Flows, Design Of Experiments, Statistical Process Control, Yield Analysis, Mask Rules, Materials, Tool Readiness, Technology Validation, Advanced Packaging, Interconnects, Data Analysis, Metrology, Hybrid Bonding, Warpage Modeling

Industry

Semiconductor Manufacturing

Description

Own package-level process integration across 2.5D/3D flows (wafer-to-wafer, chip-to-wafer, advanced interconnects), defining specs and process windows that meet high performance targets for HPC/AI products. Develop and integrate semiconductor manufacturing processes; Design, optimize, and implement fabrication flows that seamlessly integrate multiple steps (lithography, etch, deposition, diffusion, CMP, and thin films) into cohesive production processes. Design and execute DOEs on bonding, underfill, molding, stacking, and integration steps; Apply SPC to parametrics and yield detractors and close the loop with corrective actions. Analyze yield, performance, and defect data. Establish mask rules, materials, tool readiness, baseline qualification, and technology validation plans. MS or PhD in Materials Science, Chemical Engineering, or related field 10+ years experience in advanced packaging technology development (2.5D/3D, HBM) Hands-on knowledge of advanced interconnects/TSV, die stacking, underfill, molding, and bonding flows Proficiency in DOE/SPC and data analysis (e.g., JMP/Minitab/Python); demonstrated root-cause problem solving and yield improvement. Experience with metrology: SAM, Xray/CT, IR, warpage profilers (shadow moiré/DIC) Strong communication skills; ability to lead cross-functional teams and drive actions to closure in fast-paced environments. Direct experience with hybrid bonding integration and reliability (W2W/C2W) Demonstrated success in HBM and logic integration (including thermal co-optimization) Warpage modeling and inline correlation experience Deep familiarity with underfills, reworkable strategies, and TC bonding optimization

Responsibilities

The engineer will own package-level process integration across 2.5D/3D flows, defining specifications and process windows for high-performance targets. They will develop and integrate semiconductor manufacturing processes and analyze yield, performance, and defect data.