MTS Silicon Design Engineer at Advanced Micro Devices, Inc

Bush, Scotland, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

23 Aug, 26

Salary

0.0

Posted On

25 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Asic Design, Soc Design, Verilog, Systemverilog, VHDL, Microarchitecture, Simulation, Synthesis, High-speed Networking, Uvm, Formal Verification, Python, Tcl, Perl, C/C++, Performance Modelling

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER About the Team The Networking Technology & Solutions IP Group at AMD is expanding its Data Centre design teams in Edinburgh and Belfast. We architect and deliver high-performance ASIC solutions for next-generation data center networking, enabling large-scale AI training and inference clusters. Our work spans the full development lifecycle — from architecture definition and algorithm modelling through to RTL implementation, verification, and silicon validation. We operate at the intersection of networking and AI infrastructure, solving complex system-level challenges around bandwidth, latency, scalability, and power efficiency. We foster a collaborative, high-ownership culture where engineers are encouraged to work across domains and develop a holistic understanding of the system. Joining at this stage offers a unique opportunity to influence both technical direction and team culture as we continue to grow. About You: You are an experienced silicon design engineer with a proven track record of delivering complex ASICs or subsystems in high-performance networking or compute environments. You bring: Strong technical leadership and ownership of large design blocks or subsystems A system-level mindset with the ability to balance architecture, performance, power, and area trade-offs Confidence in making high-impact technical decisions and influencing cross-functional teams A collaborative approach, working effectively across geographies and disciplines You are motivated by solving challenging problems in AI-scale networking systems and are passionate about delivering high-quality silicon that directly impacts real-world workloads. About the Role: As a senior member of the design team, you will: Lead the design and delivery of complex ASIC blocks for data center networking silicon Contribute to and influence architecture definition and microarchitecture decisions Translate system requirements into detailed specifications and high-quality RTL implementations Work closely with verification, physical design, and validation teams to ensure first-silicon success Drive quality, power, and area optimization across the design Mentor junior engineers and contribute to engineering best practices Collaborate across global teams to align on technical direction and execution Qualifications: Bachelor’s, Master’s, or PhD in Electronic Engineering, Computer Science, or a related field Skills and Experience: Required 10+ years of experience in ASIC/SoC design Strong expertise in Verilog/SystemVerilog (or VHDL) Proven experience delivering complex digital hardware systems to silicon Solid understanding of microarchitecture and hardware/software trade-offs Experience with industry-standard ASIC design, simulation, and synthesis flows Strong debugging, analytical, and problem-solving skills Preferred Experience in high-speed networking, data center, or AI infrastructure silicon Knowledge of networking protocols (e.g., Ethernet, RDMA, congestion control) Experience with UVM, formal verification, or advanced verification techniques Proficiency in scripting (Python, TCL, Perl, or C/C++) Experience with performance modelling or architectural simulation Familiarity with CPU/GPU architectures or heterogeneous compute systems Exposure to AI/ML workloads and infrastructure Experience leveraging AI-assisted design or productivity tools Personal Attributes Strong communicator with the ability to convey complex technical ideas clearly Self-motivated with a high degree of ownership and accountability Comfortable working in a fast-paced, evolving technical environment Collaborative team player with a growth mindset Passionate about semiconductor and digital design #LI-CY1 #Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Lead the design and delivery of complex ASIC blocks for data center networking silicon. Translate system requirements into detailed specifications and high-quality RTL implementations while mentoring junior engineers.