MTS Silicon Design Engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

07 Jul, 26

Salary

0.0

Posted On

08 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Verilog Hdl, System Verilog, Amba Bus, Front-end Design, Synthesis, Sta, Network-on-chip, Low Power Design, Perl, Python, Micro-architecture, Rtl Design, Timing Closure, Problem-solving, Communication Skills

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Control Fabric (CF) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of System reset and boot, network-on-chip, data compression, advanced power management, clocking, etc. The SRDC CF team is a critical part of global CF team. THE PERSON: Candidate will work as design engineer in CF team on development of industry leading control fabric. KEY RESPONSIBILITIES: Block level micro-achitecture spec, RTL design, synthesize and timing closure Collaborate with verification team to achieve good coverage Deliver CF IP to multiple SoCs, meeting power, area, timing schedule bounding box and other metrics PREFERRED EXPERIENCE: Strong skills on Verilog HDL or System Verilog Strong knowledge on AMBA bus Familiar with Front-end design and implementation flow Knowledge on synthesis and STA Network-on-chip experience is a plus Low power design experience is a plus Good skills on Perl/Python script Strong analytical and problem-solving skills Excellent communication skills and experience collaborating with other engineers Fluent English skills (listening, speaking and writing) ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-EH1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The engineer will be responsible for block-level micro-architecture specification, RTL design, synthesis, and timing closure. They will also collaborate with the verification team to ensure high coverage and deliver IP to multiple SoCs while meeting power, area, and timing metrics.