Start Date
Immediate
Expiry Date
25 May, 26
Salary
0.0
Posted On
25 Feb, 26
Experience
2 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
RTL Implementation, Verilog, VHDL, Linting, CDC Analysis, Synthesis, Static Timing Analysis, SystemVerilog UVM, RISC Processor Architecture, AMBA Protocols, AXI, AHB, APB, Perl, Python, C++
Industry
Semiconductor Manufacturing