Network On Chip Verification Engineer at Advanced Micro Devices Inc
Boxborough, MA 01719, USA -
Full Time


Start Date

Immediate

Expiry Date

27 Jul, 25

Salary

0.0

Posted On

27 Apr, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Mentor Graphics, Cadence, Architecture

Industry

Information Technology/IT

Description

PREFERRED EXPERIENCE:

  • Project level experience with design concepts and RTL implementation for same
  • Experience with functional verification tools by VCS, Cadence, Mentor Graphics
  • Good understanding of computer organization/architecture
Responsibilities

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

As a Design Verification Engineer on the Infinity Fabric verification team you join a dedicated team whose work has enabled AMD to put multiple SoCs to market each year. The ground-breaking Fabric IP verified by this team is flexible and scalable and is integral to every new AMD product being developed across Ryzen, Epyc, Instinct, Radeon and Semi-Custom markets. This is your chance to be a part of this unique team!

KEY RESPONSIBILITIES:

  • Develop and enhance UVM-based testbenches to verify new features for a state-of-the-art industry leading Data Fabric IP for AMD’s CPUs, GPUs and APUs
  • Work closely with other verification engineers, designers, architects, and performance engineers to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
  • Execute test plans for constrained-random and directed tests, new checks and functional coverage
  • Write tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design
  • Responsible for verification quality metrics like pass rates, code coverage and functional coverage
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