Neuromorphic Silicon Design Engineer at Intel - Dubai

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

25 Apr, 26

Salary

269100.0

Posted On

25 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Neuromorphic Computing, AI, ASIC Design, SoC Design, RTL Design, Asynchronous Design, Performance Modeling, Vendor IP Integration, Test Plan Review, Debugging, Physical Design, Low Power Implementation, Security Design, Customer Enablement, Collaboration, Optimization

Industry

Semiconductor Manufacturing

Description

Job Details: Job Description: The Opportunity For nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads. Position Overview We are growing our silicon team, seeking experienced designers passionate about innovation at the intersection between emerging semiconductor technology and novel computing paradigms. As a member of Intel's neuromorphic silicon team, you will contribute across a range of design levels, methodologies, and features, from architecture modeling to RTL design to asynchronous circuits across processing cores, memory, networking, and interfaces. Candidates should be familiar with accelerator design, sensor technologies, Ethernet, and AI workloads. You should be comfortable with performance modeling, collaborating with architects and algorithms researchers, and optimizing designs for power/performance/area. An openness to learning new technologies and methodologies, such as asynchronous design, is essential. Responsibilities • Model, prototype, and document new features for improving product KPIs and expanding workload breadth. Evaluate tradeoffs in partnership with architects and algorithms researchers. • Evaluate, select, and integrate vendor IP especially for chip/chiplet interfaces. • Enter RTL and asynchronous design (CSP/CAST) optimized for synthesis and place-and-route closure. • Work with system software developers and architects to define runtime, boot, reset, and power management modes and requirements. • Review test plans and work with verification engineers to debug regression/test failures. • Work with physical design engineers on floorplans, timing constraints, and post-layout timing issues. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum qualifications • Bachelors & 9+ years or Masters & 6+ years or PhD & 4+ years with an engineering degree and hands-on design experience. • 4+ years of experience in SoC accelerator or ASICs design. • 4+ years of experience entering new designs from architecture specifications. • History of enabling production quality silicon. Preferred qualifications • Experienced in neuromorphic computing and AI/ML accelerator design. • Experience with standard IO interfaces, PHYs, and protocols such as Ethernet, PCIE, MACsec/IPsec, RoCEv2, MIPI CSI-2, JESD204. • Experience with Low power/UPF implementation/verification techniques. • Experience with pre-silicon customer enablement on FPGA emulation platforms. • Experience with security design and requirements, such as Root of Trust (RoT), secure boot, cryptographic acceleration, and FIPS. • Experience leading silicon design/verification teams. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

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Responsibilities

The role involves modeling, prototyping, and documenting new features to improve product KPIs, as well as evaluating tradeoffs with architects and researchers. Additionally, the engineer will work on RTL and asynchronous design, collaborating with software developers and verification engineers.