Packaging Engineer at Cambridge GaN Devices

Cambridge, England, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

04 Jun, 26

Salary

0.0

Posted On

06 Mar, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Semiconductor Packaging, GaN Power Products, Multiphysics Simulation, Finite Element Modelling, 3D CAD, Thermal Characterisation, Product Qualification Tests, Failure Analysis, Wirebond, Flip Chip, Embedded Packages, Design Process Enhancement, Problem-Solving, 8D, DOE, Fishbone Diagrams

Industry

Semiconductor Manufacturing

Description

Packaging Engineer (GaN) Team – R&D Engineering Location – Cambridge, UK Contract – Full-time, Permanent About CGD Making Sustainable Power Electronics Possible A spin-out of the Cambridge University, Cambridge GaN Devices (CGD) is a fabless semiconductor company that develops a range of energy-efficient GaN-based power devices to make greener electronics possible. The global power semiconductor market is expected to exceed $50BN. In addition to the multi-million seed fund and Series A and now B private investments, CGD has so far successfully secured four projects funded by iUK, BEIS and EU (Penta). The technical and commercial expertise of the CGD team combined with an extensive track record in the power electronics market has been fundamental in early market traction of our proprietary technology. Bringing Innovation into Everyday Life The environmental need for solutions to resolve the world’s most significant challenges (energy consumption and CO2 emissions) inspires us to contribute to society by preserving nature with energy-efficient power solutions. With a mindset on pushing the limits of semiconductor (GaN) properties and an outstanding team of worldwide experts leveraging knowledge, IP, and decades of research, we demonstrate technological advancement by developing green solutions for everyday electronics, respecting our planet’s natural resources, and creating a more sustainable future for the generations to come. Why Work for CGD We Champion Commitment, Celebrate Empowerment, and Reward the Brave. We are interested in change-makers with a passion for power semiconductors who are willing to explore unconventional ways to meet the company’s green agenda. At CGD, we pride ourselves on putting empowerment and commitment at the core of our company culture. We offer a relaxed yet productive working environment where everybody is valued and respected and becomes part of commercial success while experiencing professional growth. If your heart beats for innovation, challenge, and growth, and if the prospect of joining a friendly and game-changing company is for you, we want to hear from you. The Opportunity CGD is now looking for a Packaging Engineer to join our growing engineering team. Reporting directly to the Director of Engineering, this is an amazing opportunity to join CGD at an early stage and help drive the packaging solutions for CGD’s GaN power products. The Engineer will be responsible for supporting the technical development of high performance and high-density semiconductor packaging solutions for CGD internal product development and public funded projects. This role will work closely with the GaN chip design team in R&D Engineering (design process), with the Operations team (packaging supply chain and support product qualification tests), and the Application Engineering team (to satisfy customers’ package requirements). The role is based in the Cambridge headquarters but may also require the post holder to travel globally to subcontractors, partners and customers. Main Responsibilities Reporting directly to the Director of Engineering, the Engineer will be responsible for: Working on the technical development of high performance and high-density semiconductor packaging solutions for CGD GaN power products Working closely with both internal (e.g. GaN chip design team, Application Engineering team, Operations team) and external (e.g. packaging partners) stakeholders, both in the UK and overseas Surveying market for suitable packaging technologies in support of CGD product roadmap Supporting package technology developments with suppliers to differentiate CGD products Conducting multiphysics simulations (finite element modelling) to analyse package and system level thermal performance, parasitic extraction, current spreading, electromagnetic fields and thermo-mechanical stress of CGD’s GaN power packages Assisting with the design of wirebond, flip chip and embedded semiconductor packages, including wafer back-end process modifications, to meet the product goals in terms of form factor as well as electrical and thermal performance Contributing to the development and enhancements of the design process, tools and methodologies to streamline the design flow for right first-time solutions Supporting semiconductor packaging verification and qualification tests, including driving the package related performance tests such as board level reliability, thermal characterisation etc Conducting first article inspection and failure analysis in the labs in Cambridge as well as with external partners Supporting the Applications Engineering team and customers by providing packaging related resources such as package outline drawings, thermal models, PCB footprints, application notes and technical support Skills and Experience Suitable candidates for the Packaging Engineers role will most likely have a background in designing and developing packages for semiconductor applications. Any experience in power related products and/or designing for GaN products would be advantageous, but not a requirement. This role might also suit a strong mechanical or electromechanical engineer, who has experience with 3D drawing, understanding the thermal aspects of design, and/or electromagnetic considerations. Essential A bachelor’s degree or higher in Engineering, Physics, Material Sciences or related subject Experience with 3D Multiphysics Simulation (e.g. COMSOL, ANSYS or similar) for thermal, electrical and stress analysis by finite element modelling Experience of producing designs according to supplier design rules with a modern 3D CAD tool (e.g. SolidWorks, Fusion360, AutoCAD or similar) A solid understanding and/or experience with the thermal characterisation of semiconductor packages Good experience with semiconductor packaging related product qualification tests such as TCoB, MSL, TC, HAST and HTS according to standards such as JEDEC, IPC, MIL, AEC-Q100 Strong problem-solving skills and the selection and use of appropriate methods such as 8D, DOE, Fishbone diagrams etc Ability to take responsibility for managing their own tasks and deliver results on time Desirable Experience in the design and manufacture of high-volume semiconductor packaging including working with overseas assembly houses In depth knowledge of power semiconductor packaging technologies, such as die-attach, Ag-sintering, flip-chip, wire bonding, PCB embedding and chip metallisation. Track record of designing and simulating semiconductor packaging for voltages larger than 100 V, ideally for GaN power devices Experience with electromagnetic finite element modelling Experience in the selection and analysis of test methods for semiconductor packaging such as CSAM, X-Ray, shear tests, CT, EDX, EMMI. Excellent salary Share options scheme available (so you own a piece of the company!) Pension scheme (6% Company contribution) Life Assurance (3x Salary) BUPA Private Medical Insurance BUPA Cash Plan (Level 3) Flexible working options (both location and times) Annual leave allowance of 33 days (including bank holidays) Training and development Electric Car Scheme Cycle to work scheme IP bonus scheme Involvement in collaborative projects and grants with University of Cambridge and other partners Recruitment referral bonus Regular social events including frequent company lunches, annual summer party, Christmas party, team building and wellbeing activities We believe in equal opportunities It takes a diverse and inclusive community of passionate, talented and committed people to build a system to shape the future of power electronics. We are committed to providing equal opportunities to all current and prospective employees regardless of age, disability, sex, sexual orientation, pregnancy and maternity, race or ethnicity, religion or belief, gender identity, or marriage and civil partnership. We believe that a more inclusive workplace, where people of different backgrounds work together, ensures better outcomes for all employees. We aspire to have a diverse workforce because, in our view, diversity enables better business outcomes. From application to interview, we place inclusion at the heart of all we do. We are well set up for collaborative hybrid working, with some members of the team working in the UK office and some from home in the UK and other cities in Europe and Asia.

Responsibilities

The Engineer will be responsible for supporting the technical development of high-performance and high-density semiconductor packaging solutions for internal product development and public-funded projects. This involves working closely with design, operations, and application engineering teams, as well as conducting multiphysics simulations and supporting qualification tests.