Packaging Engineer (Substrate Design and Layout) at Sandisk

Taichung, Taichung, Taiwan -

Full Time

Start Date

Immediate

Expiry Date

20 Sep, 26

Salary

0.0

Posted On

22 Jun, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Cadence SIP/Allegro, AutoCAD, CAM, Valor, Substrate Design, Flip Chip, Wire Bonding, 2.5D Design, FCBGA, MCM, Die Fitment Analysis, Thermal Analysis, PKG Warpage, Electrical Performance, Cross-functional Collaboration, Vendor Management

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Optimize die bonding pad, flip chip die plot, and substrate layout to streamline design complexity and reduce cost for ASIC and SiP packaging solutions, including SSD/PSSD NAND BGA, uSD, SD/SD express and USB products. Support the development and integration of new planform packaging technologies/new NAND generation, new ASIC, Emphasis is placed on interposer/substrate/board co-design, design rule definition, and cross-functional collaboration. Conduct substrate layout feasibility studies, die fitment analysis based on Org. playbook, and prepare comprehensive design documentation. Maintain and manage design libraries, and generate accurate bonding diagrams to support layout and assembly processes. Collaborate closely with hardware, assembly, and packaging engineering teams across multiple Sandisk sites to enable new product development and continuous substrate design improvement. Interface with assembly houses and substrate vendors to perform design reviews, ensure compliance with design rules, and support manufacturability. Support to department automation system developing. Qualifications REQUIRED: Master’s or Bachelor’s degree in Materials Science, Electrical/Electronics Engineering, or other relevant engineering or science disciplines. Up to 5 years of design experience in semiconductor packaging, substrate design, or related fields. Familiarity with WB version design and advanced packaging technologies such as FCBGA, MCM, or 2.5D designs is a plus. Strong foundation in design principles, materials, thermal, PKG warpage/BLR and electrical performance considerations. Ability to work collaboratively in cross-functional teams and communicate effectively across disciplines. SKILLS: Proficient in EDA tools, including Cadence SIP/Allegro, AutoCAD, CAM, and Valor for substrate and package design. Solid understanding of advanced packaging design and manufacturing processes, particularly for wire bonding, flip chip and substrate-based technologies. Listening/speaking/writing in English: Fluent~upper intermediate Strong communication and interpersonal skills to effectively collaborate across cross-functional and global teams. Familiar with substrate fabrication and manufacturing workflows, including design rule interpretation and vendor engagement. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: Packaging Engineering Location (Secondary): Taichung Office--LOC_SNDK_Taichung SNDK Office Work Location: Taichung Office--LOC_SNDK_Taichung SNDK Office

Responsibilities

Optimize die bonding pads, flip chip die plots, and substrate layouts to reduce cost and complexity for ASIC and SiP packaging solutions. Collaborate with cross-functional teams and external vendors to ensure manufacturability and support new product development.