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Packaging Substrate Engineer at Apple
, California, United States -
Full Time

Start Date

Immediate

Expiry Date

13 Feb, 26

Salary

0.0

Posted On

15 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

SoC Package Substrate Technology Development, Substrate Manufacturing, Material Development, Process Development, Spec Definitions, Cu Plating, Lithography, Dielectric Material, Via Formation, Solder Resist, Surface Finish, Package Assembly, Integration Process, Cadence Allegro, Design Review for Manufacturing, Project Management, Communication Skills

Industry

Computers and Electronics Manufacturing

Description
Our Hardware Technology Packaging team invents, designs, develops, and integrates electronic packaging solutions for Apple’s internal and custom external components of hardware for its consumer electronic products such as iPhone, iPad, Mac, Apple Watch, Apple TV etc. In this highly visible role, you will own and drive sophisticated package selection, new-generation package structure and configuration optimization. You will be responsible for Apple package substrate including design, technology, manufacturing, and reliability, and future roadmap; and work with cross-functional teams to achieve the best package performance. DESCRIPTION • Lead SoC package substrate technology development, pathfinding, and roadmap definition. • Work with substrate manufacturing industry, foundry, and OSAT to bring package substrate solution from concept to HVM. • Drive industry with sophisticated package solutions, new architecture, material and process development, and spec definitions. • 5% International travel. MINIMUM QUALIFICATIONS BS and 10+ years of relevant industry experience. PREFERRED QUALIFICATIONS MS or Ph.D. and 8+ years of relevant industry experience. Proven fundamentals in material/chemistry/mechanical engineering field(s). In-depth knowledge of substrate technology, manufacturing process, design rules, and roadmap. Hands-on experience in substrate manufacturing and technology development: Cu plating, lithography, dielectric material, via formation, solder resist, surface finish etc. Familiarity with package assembly and integration process preferred. Experience in Cadence Allegro platform tools and design review for manufacturing (DFM). Exceptional technology development & project management skills. Strong communication & collaborative skills.
Responsibilities
Lead the development of SoC package substrate technology and define the roadmap. Collaborate with cross-functional teams and the substrate manufacturing industry to optimize package performance.