Piper Companies is hiring an Packet Processor Architect with a small start up based in Saratoga, CA. The Packet Processor Architect will help define Eridu’s next-gen networking ASICs built for AI infrastructure, working closely with the CTO and top-tier designers in an intensive, collaborative environment.. The Packet Processor Architect will need to sit on site in Saratoga, CA 5 days per week.

REQUIREMENTS FOR THE PACKET PROCESSOR ARCHITECT:

• MSEE or equivalent with 15+ years in networking/datapath ASICs
• Proven background with switch/router ASICs (e.g., Cisco Silicon One, Marvell)
• Deep experience in packet processors and programmable pipelines
• Familiar with protocols like BGP, VXLAN, IPv6 Segment Routing (bonus for multiple)
• Strong in architecture modeling, performance tuning, and debugging
• Comfortable with intensive on-site collaboration

• Architect L2–L4 packet processing pipelines: ingress/egress, classification, ACLs, parsing/deparsing, and tunneling protocols (VXLAN, GRE, IPinIP)
• Design lookup engines, table management, hash structures, and metadata handling
• Define parsing, packet editing, and scheduling capabilities
• Translate system-level goals into detailed architecture specs
• Collaborate with RTL, firmware, and physical design teams
• Validate architecture via modeling and performance analysis
• Guide integration of IP blocks (e.g., TCAM, SerDes, PCIe, DMA)
• Support post-silicon bring-up, debug, and tuning
• Participate in design reviews and architecture methodology definition