KEY TAKEAWAYS

• 
  Hours
  40 hr.
• 
  Salary indication
  Salary gross/monthly
  based on full-time
  € 2,901 - € 3,707
• 
  Deadline
  29 Jun 2025
  Edge devices that can learn autonomously while guaranteeing dependability are key to the next wave of AI adoption. Within this journey, you will focus on algorithmic innovations that exploit—and are constrained by—an emerging neuromorphic processor that our hardware team is taping out. The core challenge is to co-design algorithms and architecture so that robustness, security, and energy efficiency are all first-class citizens.

As the PhD candidate for the “architecture-aware algorithm”, you will:

• Devise on-device learning rules tailored to dataflow neuromorphic cores.
• Quantify and mitigate fault modes arising from device noise, variability, radiation, and adversarial tampering.
• Build an open-source software stack that maps algorithms to hardware, including compiler extensions and runtime monitors.
• Demonstrate your solutions on real-world use cases

You will collaborate closely with hardware designers and industrial partners, benefiting from their complementary expertise and datasets. The position is embedded in the CAES chair of the EEMCS faculty, which offers a vibrant, international research environment and access to state-of-the-art fabrication and test facilities.

Please refer the Job description for details