PhD Position Reliable AI Accelerator Design in MSCA Doctoral Network TIRAMI at TU Delft
Delft, Zuid-Holland, Netherlands -
Full Time


Start Date

Immediate

Expiry Date

26 Jun, 25

Salary

2.901

Posted On

27 Mar, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Good communication skills

Industry

Electrical/Electronic Manufacturing

Description

SHAPING THE FUTURE OF RELIABLE EDGE AI

Various emerging device technologies and computing paradigms are being investigated for energy-efficient artificial intelligence (AI) applications at the edge. Some examples are RRAM, FeFET and STT-MRAM-based Computation-in-Memory (CIM) accelerators. However, these new technologies and computing paradigms introduce new challenges in terms of reliability. For instance, non-idealities such as variability, drift, read/write disturb may cause computational inaccuracy. Ensuring reliable computation in memory using emerging devices for edge AI is of great importance.
The Computer Engineering (CE) section of the Quantum & Computer Engineering (QCE) department is looking for a highly motivated PhD candidate who wants to work on reliable and fault tolerant architectures for future AI accelerators. The candidate will be part of a research team working on design, manufacturing and testing of AI accelerators using emerging devices.
You’ll be part of a diverse and passionate team of academic staff, PhD candidates, and postdocs in the Computer Engineering Section. We value open discussions, sharing ideas, and collaborating regularly to advance our understanding of computer engineering. You’ll also receive comprehensive training to support your growth as a scientist.

Responsibilities

While being an integral part of the team, you will work on the following:

  • Identify the reliability failure mechanisms and non-ideality issues in various of AI accelerators, such as emerging memory-based CIM, or spiking NNs;
  • Develop reliability solutions to address the impact of non-ideality issues.
  • Develop fault-tolerance and self-healing mechanisms to guarantee reliable system operation in the presence of faults and defects.
  • Develop design time and runtime configurable solutions for graceful degradation.
  • Integrate and validate the developed solutions in edge AI chip prototypes.

This position is a part of a new European MSCA Doctoral Network TIRAMISU “Training and Innovation in Reliable and Efficient Chip Design for Edge AI” (2024-2028) – an EU-funded program designed to train future European engineers and researchers driving innovation in reliable and energy-efficient Edge AI chips. The program provides strong interdisciplinary training, international collaboration, and mobility opportunities. Learn more at https://tiramisu-project.eu/.

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