Physical Design (Backend) Technical Leader at Intel - Dubai
Petah Tikva, Center District, Israel -
Full Time


Start Date

Immediate

Expiry Date

27 Dec, 25

Salary

0.0

Posted On

28 Sep, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

VLSI Physical Design, Power Optimization, Performance Optimization, Area Optimization, Place and Route, Timing Closure, Signal Integrity, Manufacturability, STA, IR Drop, EM Analysis, DRC/LVS, ECO Flows, Mentoring, Problem-Solving, Communication, Teamwork

Industry

Semiconductor Manufacturing

Description
Job Details: Job Description: We are seeking for a highly experienced and motivated Senior Physical Design Technical Lead to join our group and lead and drive backend implementation of advanced Intel wireless products. As part of your job you will define and improve design implementation flows, automation and signoff methodologies. Technically Lead the physical design flow and implementation activities for complex VLSI chips, ensuring high performance and reliability. Optimize power, performance, and area (PPA) metrics through advanced techniques and tools. Analyze and resolve design issues related to Place and Route, timing, power, signal integrity, and manufacturability. Collaborate with other Intel design teams to ensure seamless integration and optimization of design specifications. Mentor and guide junior engineers, providing technical expertise and support. Interface with EDA vendors to evaluate and integrate new tools and technologies and stay updated with the latest industry trends and advancements in VLSI Physical design. Qualifications: BSc/MSc in electrical or computer engineering. 10+ years of hands-on experience in VLSI physical design, with a proven track record of successful projects working with advanced technology nodes. Excellent familiarity with all Physical Design implementation flows and techniques, including floorplanning, placement, routing, and timing closure. Proficiency in Synopsys EDA tools (Cadence is an advantage). Knowledge of scripting languages such as Python, Perl, or TCL. Strong understanding of STA, IR drop, EM analysis, DRC/LVS, and ECO flows. Experience with power, performance, and area (PPA) optimization. Experience in managing and mentoring technical teams. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Petah-Tikva Additional Locations: Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

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Responsibilities
Lead and drive backend implementation of advanced Intel wireless products, defining and improving design implementation flows and methodologies. Collaborate with design teams to ensure seamless integration and optimization of design specifications while mentoring junior engineers.
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