Physical Design Engineer at Altera

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

24 Apr, 26

Salary

164700.0

Posted On

25 Jan, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, FPGA, SoC, PPA Optimization, Scripting, TCL, Python, Perl, Timing Closure, Power Analysis, Signal Integrity, DRC, LVS, ECO, Floorplanning, Routing

Industry

technology;Information and Internet

Description

Job Details: Job Description: About the Role: As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow — from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains). Key Responsibilities: Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII. Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies. Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met. Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention. Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness. Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization. Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $113,700 - $164,700 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. Qualifications: Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience in: Hands-on digital/SoC physical design (synthesis through P&R and sign-off). Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation. Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement. Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution. Power/IR analysis, signal/power integrity reporting, and corrective action planning. Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams Preferred Qualifications: Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows. Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration. Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows. Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure. Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations. Experience mentoring or leading small physical design sub-teams or owning major P&R blocks. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

Responsibilities

The Physical Design Engineer will execute physical design implementation tasks from netlist to GDSII and apply PPA optimization techniques across block-level and full-chip hierarchies. They will also collaborate with various teams to ensure design constraints are met and enhance physical design flows.