Physical Design Engineer at Apple

, California, United States -

Full Time

Start Date

Immediate

Expiry Date

26 May, 26

Salary

0.0

Posted On

25 Feb, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, PHY Design, SOC Designs, RTL, GDSII, Static Timing Constraints, Floor-planning, Power Grid, Clock Network, Place And Route, ECOs, LVS, DRC, Physical Verification, Verilog, Perl/Tcl

Industry

Computers and Electronics Manufacturing

Description

At Apple we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing, and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design. DESCRIPTION As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration. MINIMUM QUALIFICATIONS BS and a minimum of 20 years relevant industry experiences. PREFERRED QUALIFICATIONS The ideal candidate will have deep design experience in high PHY and/or SOC designs. Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route. Experience in developing and implementing Power-grid and Clock specifications. Strong understanding of all aspects of Physical construction, Integration and Physical Verification. Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes. Power user of industry standard Physical Design & Synthesis tools. Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

Responsibilities

The engineer will contribute to all phases of physical design for high-performance PHY designs, from RTL through to GDSII delivery. Responsibilities include generating timing constraints, building floor-plans, developing clock networks, and performing place and route to meet constraints.