Physical Design Engineer at Astera Labs

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

28 May, 26

Salary

0.0

Posted On

27 Feb, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Synthesis, Place And Route, CTS, Extraction Timing Analysis, STA, Physical Verification, Timing Closure, Formal Verification, GDSII, Cadence, Synopsys, System Verilog, Verilog, DFT, Python, Perl

Industry

Semiconductor Manufacturing

Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred. 4-15 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience: Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Responsibilities

The role involves hands-on, thorough knowledge of backend physical design tools and methodologies for advanced process nodes, focusing on synthesis, place and route, and timing analysis. Responsibilities include driving complex designs from architecture through to GDSII for both block and full-chip levels.