Physical Design Engineer at Cisco - Mozambique

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

12 Sep, 26

Salary

277600.0

Posted On

14 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL-to-GDSII, Floor Planning, Static Timing Analysis, Place and Route, Clock and Power Distribution, Timing Convergence, ASIC Design, Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, AI Prompting

Industry

Software Development

Description

The application window is expected to close on: 07/31/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will: Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies. Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools. Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements. Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency. Evaluate and implement new timing methodologies; provide creative debugging solutions. Contribute to best practices and drive methodology alignment across projects. Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC Design experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC Design experience, or PhD in Electrical or Computer engineering + 1 year of ASIC Design experience Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies. Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus. Preferred Qualifications Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment. Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis. Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions. Experience with custom clock (H-Tree or Mesh) at chip level. Experience with Python and usage of AI tools by giving accurate prompts Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $137,000.00 to $200,500.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $165,000.00 - $277,600.00 Non-Metro New York state & Washington state: $146,700.00 - $247,000.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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Responsibilities

Drive the full RTL-to-GDSII implementation flow for advanced semiconductor nodes, focusing on floor planning and timing optimization. Collaborate with cross-functional teams to deliver high-performance networking chips and improve backend design methodologies.