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Physical Design Engineer - HBM Layout at Micron Technology

Tlaquepaque, jalisco, Mexico -

Full Time

Start Date

Immediate

Expiry Date

03 Feb, 26

Salary

0.0

Posted On

05 Nov, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Layout Design, MOS Basics, Fabrication Fundamentals, Analog Layout Basics, DRC, LVS, Physical Verification, Interpersonal Skills, Problem-Solving, English Communication, Electronics, Cadence VLE/VXL, Mentor Graphic Calibre, Python, C++, Simulation Tools

Industry

Semiconductor Manufacturing

Description

Responsible for Layout design of leaf cell/Stdcell or sub block Have concepts of MOS basics, fabrication fundamentals and Analog layout basics Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Demonstrate commitment towards the work/assignment and takes proactively measure to finish the work on time. Can interpret the DRC/LVS/ and other physical verification checks Effectively communicating with Internal teams to assure the success of layout project. Bachelor's degree, master or PHD in Electrical, Electronics, Mechatronics, Robotics Engineering, Nanotechnology or similar. Graduated within the last 2 years from a Bachelor's degree, master's degree, or PhD program. Strong knowledge layout effects on the circuit such as speed, capacitance, power and area Effective interpersonal and problem-solving abilities. English language communication skills (conversational level is a must). Participated internships or school projects related to electronics and cadance VLE/VXL and Mentor Graphic Calibre DRC/ LVS A self-motivated, enthusiastic team player who enjoys working with others Passionate about Technology, willing to learn and develop into the semiconductor field. Knowledge of Pre-silicon areas such as RTL design, verification, analog circuit and physical design. Attitude for attaining problem- solving skills and physical verification of custom layout. Experience with a programming language such as Phyton / C++, Phyton Used Cadence VLE/VXL, Mentor Graphic Calibre DRC/LVS or similar tools. Understand layout effects on the circuit such as speed, capacitance, power and area Attitude for attaining problem-solving skills in physical verification of custom layout. Experience using simulation and design tools

Responsibilities

Responsible for layout design of leaf cell/Stdcell or sub block. Effectively communicate with internal teams to assure the success of layout projects.