Physical Design Engineer at NVIDIA

Yokneam Ilit, Haifa District, Israel -

Full Time

Start Date

Immediate

Expiry Date

23 Jun, 26

Salary

0.0

Posted On

25 Mar, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

High-Speed IP Integration, Chiplet Floorplan Layout Design, Data Curation, Dashboard Building, AI Agents Development, Scripting, Python, Tcl, Congestion Resolution, DRC Hotspot Resolution, QoR Improvement, Physical Design Tools, RTL2GDS, Linux, Data Parsing, Debugging

Industry

Computer Hardware Manufacturing

Description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. At NVIDIA Networking, we are driven by innovation and excellence. Our team in Israel is looking for a dedicated Chiplet Layout owner to join us in defining the next era of AI's networking. This is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. If you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you! What you'll be doing: Be part of a cross-business-unit team and own the high-speed IP integration. Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff. Collect and curate PD data (timing/congestion/DRC/route metrics) and build dashboards or summaries to highlight trends and regressions. Develop AI agents, scripts and lightweight tools (Python/Tcl) to automate run setup, log parsing, QoR comparison, and root-cause analysis. Help resolve congestion, utilization, DRC hotspots, and improve QoR through iterative optimization. Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence. Define and implement efficient, high-quality Full Chip/Chiplet physical design tools, flows, and methodologies. Gain hands-on experience implementing the partition-level BE design (RTL2GDS). What we need to see: BS/MS. in Electrical Engineering or Electrical Practical Engineer certificate, or equivalent experience. Great teammate, responsible, and motivated. Experience with Linux and scripting (Python preferred; Tcl a plus). Comfort working with data: parsing text reports, using pandas/NumPy or equivalent, producing plots/summaries. Good debugging skills and ability to communicate findings clearly. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

The role involves owning high-speed IP integration and building Chiplet floorplan layout designs from initial planning through implementation and signoff. Responsibilities also include developing automation tools and resolving physical design issues like congestion and DRC hotspots.