Physical Design Lead, Bangalore at Eridu AI

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

30 May, 26

Salary

0.0

Posted On

01 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, SoC, Floorplanning, Timing Closure, Power Optimization, Sign-off, CTS, Routing, ECO Implementation, PPA Optimization, IR/EM, TCL, Python, Perl, Shell, Synopsys Fusion Compiler

Industry

Computer Networking Products

Description

Position Overview We are seeking a hands-on Technical Lead, Physical Design to drive end-to-end implementation of complex SoC designs at advanced process nodes. This role combines deep technical execution with team leadership and cross-functional collaboration. The ideal candidate is a seasoned physical design expert who has led high-complexity, production tape-outs and can independently drive floorplanning, timing closure, power optimization, and sign-off. In addition to owning critical blocks and chip-level integration, this leader will mentor engineers, establish best practices, and represent physical design in architecture and cross-functional reviews. This is a high-impact role within Eridu’s silicon organization, supporting next-generation AI infrastructure devices built at advanced nodes (7nm, 5nm, and 3nm-class technologies). Key Responsibilities Lead full-chip and/or large-block physical design execution from netlist to GDSII. Own critical aspects of implementation including floorplanning, power grid design, placement, CTS, routing, ECO implementation, timing closure, and physical sign-off. Drive PPA (performance, power, area) optimization across complex SoC designs. Resolve congestion, IR/EM, multi-voltage domain, and advanced-node design challenges. Partner closely with RTL, architecture, STA, DFT, package, and foundry teams to ensure clean handoff and tape-out success. Establish and improve physical design methodologies, flows, and automation. Mentor and technically guide junior and mid-level physical design engineers. Represent the physical design function in design reviews and cross-functional decision forums. Coordinate with CAD/EDA vendors to optimize tools and flows where necessary. Required Qualifications Education Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline. Master’s or Ph.D. strongly preferred. Experience 15+ years of hands-on ASIC/SoC physical design experience. Proven record of successful production tape-outs at advanced nodes (7nm, 5nm, and sub-3nm such as N3/N3E/N3P). Experience implementing high-complexity SoCs with multi-tens-of-millions of standard cell instances. Technical Expertise Deep understanding of the complete physical design flow: floorplanning, power grid architecture, placement, CTS, routing, ECOs, timing closure, and sign-off. Strong knowledge of advanced node design challenges including: PPA optimization Power and clock domain management Congestion mitigation IR drop and electromigration Low-power implementation techniques Expertise with industry-standard EDA tools such as: Synopsys IC Compiler / Fusion Compiler Cadence Innovus PrimeTime STAR-RCX Calibre Voltus Proficiency in scripting and automation (TCL, Python, Perl, Shell). Preferred Qualifications Direct experience with TSMC advanced nodes (N5, N3, N3E, N3P) and associated design rule constraints. Experience integrating high-speed IP such as SERDES, UCIe, PCIe, and similar interfaces. Familiarity with physical verification flows and debugging complex DRC/LVS/antenna/ERC issues. Experience collaborating with foundries and EDA vendors on flow optimization. Exposure to AI, networking, or high-performance compute SoCs is a plus. Leadership Expectations Lead by example as a hands-on technical authority. Define and communicate physical design best practices across the organization. Provide structured mentorship and technical reviews. Make sound technical decisions under aggressive schedules. Effectively collaborate with geographically distributed teams and external partners. Why Join Us? At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Responsibilities

This role involves leading the end-to-end physical design execution from netlist to GDSII for complex SoC designs, owning critical implementation aspects like floorplanning, power grid design, and timing closure. The lead will also be responsible for driving PPA optimization, resolving advanced node challenges, and mentoring junior engineers.