Physical Design Methodology Engineer at Advanced Micro Devices, Inc

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

06 Feb, 26

Salary

0.0

Posted On

08 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, SOC Design, Timing Analysis, Clock Tree Synthesis, Formal Verification, Physical Verification, ECO Strategy, Statistical Timing Analysis, Scripting, Machine Learning, Data Analysis, Collaboration, Debugging, Automation, ASIC Design, CAD Development

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Graphics and Engineering group, you will help bring to life cutting-edge designs related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Physical design and signoff methodology development for advanced nodes and High performance Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis. Block and top level Formal verification, Physical Verification and chip finishing methodologies. Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements Developing and Integrating ML and LLM applications for Physical Design and Analysis flows Performing data analysis and identifying design trends Customizing and implementing solutions for new challenges Collaborating with multi-site engineering teams to reach project goals Hands-on in reference flows, excellent debugging skills. Maintain and update technology collaterals PREFERRED EXPERIENCE: Experience in ASIC Physical Design and/or CAD development Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus, Cerebrus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc. Experience in 5nm and below technologies Script development, scripting (TCL, Perl, Python, Pandas), ML/AI techniques Knowledge and Experience in ML and LLM Experience with data analytics applications, database management ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA #LI-PA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities

The role involves developing physical design and signoff methodologies for advanced nodes and high-performance computing SOCs. The engineer will collaborate with various teams to ensure first pass silicon success and improve design PPA.