CAPGEMINI ENGINEERING

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

• Overseeing all aspects of Physical Design at either the full chip or block level, particularly in highly advanced technology nodes (10nm and below).
• Engaging deeply in floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, and place and route.
• Handling all relevant activities related to timing analysis, ensuring closure through sign-off, including SI/noise, and performing ECO tasks (both functional and timing).
• Leading validation/qualification tasks such as Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.
• Contributing to the overall development and implementation of Low Power solutions.
• Developing/enhancing timing-related scripts for tasks like clock skew analysis, critical path analysis, various IO interfaces, and constraints partitioning/budgeting (from top-level to block level).
• Successfully completing multiple design cycles of high complexity with minimal supervision.