Physical Design SoC Clock Engineer at Intel - Dubai

, , United States -

Full Time

Start Date

Immediate

Expiry Date

21 Mar, 26

Salary

262680.0

Posted On

21 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, SoC Design, RTL, GDS, Synthesis, Place And Route, Clock Tree Synthesis, Static Timing Analysis, Power Distribution, Clocking Techniques, Low-Power Clocking, Scripting, Signal Integrity, Electromigration, Power Integrity

Industry

Semiconductor Manufacturing

Description

Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required. Builds simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation. Creates scalable flows for clocking infrastructure for better performance and power in the design. Interacts with architecture and IP/SoC design teams to understand clocking requirements and helps them in deciding the right clock distribution methodology based on power and performance requirements. This position offers work remotely if not co-located at the Fort Collins, CO site. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This is not eligible for Intel Immigration sponsorship. Minimum Qualifications: Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 5+ years of relevant experience -OR- Master's in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 4+ years of relevant experience Relevant experience should include the following: 4+ years of experience hands-on experience across the entire spectrum of RTL to GDS implementation on advance semiconductor technology nodes and specific challenges in clock design. 4+ years of experience in Clocking techniques, static timing analysis (STA), clock domain crossing (CDC) checks, jitter/skew analysis and low-power clocking strategies. Preferred Qualifications: Experience with scripting skills in Tcl, Perl, or Python for automation and flow enhancements Understanding of signal integrity, electromigration, and power integrity in the context of clock networks. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: Virtual US Additional Locations: Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003 Annual Salary Range for jobs which could be performed in the US: $139,710.00-262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/28/2025 Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

How To Apply:

Incase you would like to apply to this job directly from the source, please click here

Responsibilities

The role involves physical design implementation of custom IP and SoC designs from RTL to GDS, ensuring the design database is ready for manufacturing. It includes conducting clock analysis, supporting power grid methodologies, and interacting with design teams to meet clocking requirements.