Physical Design Technical Lead/Engineer at Altera

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

01 May, 26

Salary

206500.0

Posted On

31 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Digital Design, SoC Design, EDA Tools, Scripting, Power Analysis, Timing Closure, DFT, Manufacturing, Mentoring, Automation, Verification, Debugging, Collaboration, Optimization, Integration

Industry

technology;Information and Internet

Description

Job Details: Job Description: About Altera Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation. Our innovation in programmable logic began in 1983. Since then we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets. Join us on our journey to becoming the world’s #1 FPGA company! About the Role As a Sr. Physical Design Technical Lead/Engineer at Altera, you will play a critical role in our backend implementation flow - from RTL/netlist through to GDSII/tape-out for FPGA/SoC devices. You will interface with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve our performance/power/area (PPA) goals, with particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains). Key Responsibilities Lead and execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII. Apply PPA optimization techniques (performance / timing closure, power reduction, area efficiency) across blocks or full-chip hierarchies. Collaborate with front-end design, architecture, CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets and DFT Insertions are met. Develop and improve physical design flows, methodologies, scripts and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR and reduce manual intervention. Participate in timing, power, EM/IR integrity, signal/power noise, DRC/LVS/ERC verification and sign-off readiness. Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization. Work closely with manufacturing and packaging partners to ensure implementation is manufacturable (DFM/DFY), meets yield targets and meets high-volume production requirements. Debug physical design issues, interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds. Mentor and collaborate with junior engineers; contribute to reviews, documentation of flows, and continuous process improvement. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $142,600 - $206,500 USD We use artificial intelligence to screen, assess, or select applicants for the position. Qualifications: Minimum Qualifications: Bachelor’s in Electrical Engineering, Computer Engineering or related field with 10+ years of experience in the following skills: Hands-on experience in digital/SoC physical design (synthesis through P&R through sign‐off). Experience with industry‐standard EDA tools (e.g., Synopsys IC Compiler/ Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high speed digital ASIC/SoC implementation. Scripting/programming experience (TCL, Python, Perl, shell) for flow automation and productivity enhancement. Physical design flow experience: floor-planning, CTS, placement, routing, gating power domains, clock domain crossing, multi-power domain design, timing closure, ECOs, DRC/LVS/DFM issues. Experience in power/IR analysis, signal/power integrity reports, and propose corrective actions. Experience interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, manufacturing and packaging teams. Preferred Qualifications Hands on experience in the following tools: Primetime (Tempus) Fusion Compiler (ICC/ICC2/Innovus) Calibre Conformal (Formality) Redhawk (Voltus) Tetramax/Tessent Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

Responsibilities

Lead and execute physical design implementation tasks from netlist to GDSII. Collaborate with various teams to ensure design constraints and performance goals are met.