Physical Synthesis CAD Engineer at Apple

Cupertino, California, United States -

Full Time

Start Date

Immediate

Expiry Date

16 Jul, 26

Salary

0.0

Posted On

17 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Synthesis, RTL, GDS Signoff, TCL, Python, Perl, Fusion Compiler, Genus, CAD Flow Development, UPF, Conformal LEC, Formality, Static Timing Analysis, Linting, Place and Route, Low Power Implementation

Industry

Computers and Electronics Manufacturing

Description

Do you want to directly impact the performance of every iPhone, iPad, and Mac? You'll push the boundaries of physical synthesis for Apple's cutting-edge processors, solving problems that determine whether our next-generation CPUs, GPUs, and NPUs can deliver breakthrough performance while maintaining industry-leading power efficiency. DESCRIPTION You'll own the synthesis challenges that matter most to Apple Silicon. You will apply your hands-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. As the synthesis and flow expert, you'll partner closely with design teams to define what works best for their specific challenges. You'll develop the methodologies, tools, and optimized flows that enable design teams to achieve breakthrough PPA results. You'll push beyond conventional synthesis limits - developing innovative techniques and proving their effectiveness by running full validation flows from RTL through place-and-route and timing signoff to show actual PPA improvements. Your optimizations will directly translate to faster, more efficient Apple devices. You'll work directly with EDA vendors to shape tool roadmaps, build custom solutions for problems that push beyond industry standards, and see your work ship in millions of devices. MINIMUM QUALIFICATIONS Experience with TCL, Python or Perl scripting languages Minimum requirement of BS PREFERRED QUALIFICATIONS Experience with industry standard Synthesis tools such as Fusion Compiler or Genus Experience working with CAD Tools & flow Experience in CAD flow or FE methodology development Experience with Low Power implementation flows (UPF) is a plus Experience with logical equivalence tools such as Conformal LEC and/or Formality is a plus Experience in linting, static timing analysis, low power checks (UPF) or place and route tools is a plus Proficiency with TCL, Python or Perl scripting languages strongly preferred

Responsibilities

You will own synthesis challenges for Apple Silicon, developing and improving implementation flows from RTL through GDS signoff. You will partner with design teams to create innovative methodologies and tools that optimize PPA results for next-generation processors.