PLL Design Engineer at Apple

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

13 Jul, 26

Salary

0.0

Posted On

14 Apr, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

PLL Design, VCO Design, RF Circuit Design, Mixed-signal Design, Transistor-level Feasibility, Phase Noise Optimization, Jitter Analysis, Cadence Virtuoso, SpectreRF, Matlab, VerilogA, Fractional-N PLL, Digital PLL, Sigma-delta PLL, Device Physics, RF Transceiver Architectures

Industry

Computers and Electronics Manufacturing

Description

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal candidate will possess strong analytical abilities, a passion for innovation, and extensive experience in designing and implementing PLL architectures and circuits. In this highly visible role, you will drive innovation within a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. DESCRIPTION Our team is responsible for all aspects of silicon development for cellular transceivers, with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. You will utilize your virtuoso knowledge to design PLL Circuits and component blocks including some of the following: PLL, VCO, LO generation, Dividers, Charge Pumps, XTAL, and other RF/mixed-signal blocks. In addition to the above responsibilities, you will utilize your technical analysis skills to conduct transistor-level feasibility studies for new RF circuit architectures, as well as be responsible for simulation and modeling to design and develop analog and mixed signal solutions for next-generation wireless chips. MINIMUM QUALIFICATIONS BS and 10+ years of relevant industry experience required. PREFERRED QUALIFICATIONS Experience designing fractional-N PLLs, Digital PLLs, sigma-delta PLLs, and VCOs. Strong knowledge of loop design to optimize for phase noise/jitter, lock time, reference spur, area, power, etc. Understanding of device physics and demonstrated ability to apply that to optimize noise, power, area, frequency of PLL blocks. Knowledge of bandgaps, bias, opamps, LDOs, feedback, and compensation techniques. Should be familiar with Cadence Virtuoso, SpectreRF, and/or C/Matlab/VerilogA modeling. Familiarity with various RF transceiver architectures and their trade-offs is considered a plus. Bring-up and debugging skills, and experience in working with production test engineers to build test plans and design for testability. Ability to stay up to date with industry trends and new technologies to drive continuous improvement. Familiarity with digital design, digital verification, and system-verilog modeling. Familiarity with AI/ML optimization and automation flows.

Responsibilities

You will design and implement PLL architectures and component blocks such as VCOs, LO generation, and charge pumps for cellular transceivers. Additionally, you will conduct transistor-level feasibility studies and perform simulation and modeling for next-generation wireless chips.