At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that have not been solved yet? Do you like to change the game? We have an opportunity for a results-oriented and highly committed experienced Design Verification Engineer to join out team! As a member of our multifaceted group, you will have the outstanding and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with our team of Digital and Analog Design engineers. The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

DESCRIPTION

• You will develop verification plans in coordination with design leads and architects. - You’ll be responsible for building and maintaining verification test bench components and environments. - Generate directed and constrained random tests. - Run simulations and debug design and environment issues. - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. - Craft automated verification flows for block and chip level verification. - Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs. - Work with other block and core level engineers to ensure a flawless verification flow.

MINIMUM QUALIFICATIONS

• Bachelors in EE or related field, or equivalent work experience
• Excellent communication and interpersonal skills, combined with the ability to collaborate
• Ability to work well on a team, take ownership and motivate self and others
• Fluent English skills

PREFERRED QUALIFICATIONS

• Sophisticated knowledge of SystemVerilog and UVM
• Experience developing scalable and portable test-benches
• Experience with constrained random verification environments
• Experience defining coverage space, writing coverage model, analyzing results
• Experience with Assertion Based Verification
• Good Knowledge of Object Oriented Programming
• Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
• Experience with Python, Perl or TCLGood understanding of digital design and basic knowledge of mixed signal verification
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Please refer the Job description for details