ABOUT SIFIVE

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

JOB DESCRIPTION:

Sifive is looking for hardware engineers who will be responsible for defining Low Power architecture and drive the micro architecture, design, development for Core IPs. Candidates will be collaborating across Architecture and RTL teams to establish methodologies, workflows & processes to ensure efficient Energy tracking. Responsibilities also include defining the power budget/spec for IPs, and coming up with new micro architecture initiatives, rolling up of the power numbers and maintaining the chip power dashboard for various applications. Use existing workflows to analyze Energy and make high ROI RTL modifications to improve Energy. Work with logic teams to determine the correct functionality or enhance functionality for power reduction. Select and run a wide variety of workloads for power analysis. Develop IP power model on new architecture design, providing power data for performance/power/area treads-offs. Work with multi-functional teams on improving power modeling. A diverse set of knowledge in low power architecture, micro-architecture, Design, Power Intent/implementation, power optimization and power estimation would be a huge plus.

Requirements

• Experience in out of order core or accelerators uArch is highly desirable.
• Experience in leading team of engineers and driving multiple projects
• Experience with power simulation and modeling. Power modeling with emulation would be a huge plus.
• Experience with ASIC power analysis and optimization.
• Experience with script writing in Python, Perl or Tcl.
• Experience with power impact at architecture, logic design, and circuit levels.
• Excellent problem solving skill and ability to work in a dynamic and diverse environment.
• Strong organizational and communication skills as the candidate will be presenting power status to management, sales and product teams frequently.

Please refer the Job description for details