Principal ASIC/FPGA Design Verification Engineer at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

04 Feb, 26

Salary

0.0

Posted On

06 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design Verification, FPGA Verification, Verilog, System Verilog, SVA, UVM, Timing Analysis, Testbench Development, Root-Cause Analysis, Standard Protocols, Perl, Python, Problem-Solving, Communication Skills, Version Control Systems, Innovation

Industry

Semiconductor Manufacturing

Description

Job Description BE/ME in ECE, Electronics, or equivalent 8-13 years of experience in RTL design verification for Block/IP/Sub-system/SOC Knowledge in synthesis and timing analysis Experience with FPGA verification - Advantage Experience & Knowledge with verilog and System Verilog for Verification , SVA, UVM - Strong Advantage Deep knowledge of the following tools is an advantage: cadence NCSim, simvision, vmanager, any simulator, and waveform debug EDA tools from mentor, Synopsys Knowledge simulation environment System Verilog - UVM based – advantage Developing testbench for constraint random environment, Metric driven verification Root-cause design issue and able explain in text form clearly with design knowledge. Experience in standard protocols such eMMC, UFS, USB, PCIe, and DDR4 – advantage Knowledge with Perl/python – advantage Problem-solving: Ability to break the problem into small parts and apply relevant techniques to drive required outcomes Good communication and/or interaction skills among groups - local and abroad Ability to communicate multiple interfaces inside the company innovation : able to use technology in new ways to create more efficient organization and improve alignment between technology initiatives and business goals. Familiar with version control systems such as Git Qualifications BE/ME in ECE, Electronics, or equivalent 8-13 years of experience in RTL design verification for Block/IP/Sub-system/SOC Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying

Responsibilities

The Principal ASIC/FPGA Design Verification Engineer will be responsible for RTL design verification for Block/IP/Sub-system/SOC. They will develop testbenches for constraint random environments and perform root-cause analysis of design issues.