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Principal Design Engineer, ASIC at Micron Technology
Richardson, Texas, United States -
Full Time

Start Date

Immediate

Expiry Date

23 Jan, 26

Salary

0.0

Posted On

25 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

ASIC Design, SoC Architecture, Memory Technologies, Storage Controllers, High-Speed Interfaces, Performance Modeling, Hardware/Software Co-Design, RTL Design, Verilog, Error Correction Coding, Chiplet Architectures, HBM Integration, C++, Python, Collaboration, Leadership

Industry

Semiconductor Manufacturing

Description
Define and develop chiplet-based ASIC SOC architectures for memory and storage controllers, utilizing DRAM, NAND, and emerging non-volatile memory technologies. Architect and model data path, control path, cache design, and IO interface logic for high-speed memory access and management. Collaborate with firmware, system, and packaging engineering teams to ensure end-to-end system optimization. Drive performance, power, and area (PPA) trade-off analysis using modeling and simulation tools. Specify and evaluate IP blocks such as ECC engines, DMA controllers, memory interfaces (e.g., DDR, LPDDR, ONFI, UCIe, PCIe, NVMe), and die-to-die communications modules. Lead architecture reviews, contribute to design specifications, and guide RTL and verification teams. Stay current with memory and storage standards, interconnect protocols, and emerging technologies. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in ASIC/SoC architecture, preferably in memory, storage, or interconnect protocols. Strong understanding of memory technologies (e.g., DRAM, NAND) and controller architectures. Experience with high-speed interfaces (e.g. UCIe, HMB, DDR, LPDDR, PCIe, NVMe, ONFI) and PHYs. Proficiency in performance modeling, hardware/software co-design, and system-level architecture. Ability to interface with internal partners and external vendors to define memory and IO technology requirements 10+ years of experience with RTL design, Verilog, and hardware modeling tools. Exposure to AI/ML workloads, data center storage, or automotive-grade memory systems. Experience with error correction coding (ECC). Knowledge of chiplet architectures and HBM integration Strong communication and leadership skills with a collaborative mindset. Programming skills including C++ and Python.
Responsibilities
Define and develop chiplet-based ASIC SOC architectures for memory and storage controllers. Collaborate with firmware, system, and packaging engineering teams to ensure end-to-end system optimization.