Principal Design for Debug Execution Lead at Microsoft

Redmond, Washington, United States -

Full Time

Start Date

Immediate

Expiry Date

23 Feb, 26

Salary

0.0

Posted On

25 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Debug IPs, SoC Integration, Verilog, System Verilog, Scripting, Front-End Tools, Linting, CDC Checkers, Low Power Static Checkers, Clock Crossing Techniques, UPF, Post-Silicon Debug, Validation, Debug Architecture, Problem Solving, Team Collaboration

Industry

Software Development

Description

In this role on the team, your responsibilities will include: Define the micro-architectural implementation spec for debug IP's, fabrics & implement the micro-architectural specification in Verilog or System Verilog. Lead a team of engineers for IP & product DFD deliverables and support individual contributors in their own career growth. Refine Debug execution methodology and use of industry/home-grown tools to ensure design quality, effectiveness & speed up execution. Hold a primary role in enabling silicon by working directly with validation & fleet engineers to bring up debug capabilities and to help with diagnostics & screening. Work closely on Debug tool POC & roadmap associated with the RTL features implemented in design. Assess and then refine the implementation for debug coverage, area, power and performance. Ensure quality with checks covering Lint, CDC, Low Power intent and more. Delight your customers by delivering cutting-edge debug IP's & infrastructure for custom SoC designs that can perform complex and high-performance functions. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Efficient in designing debug IP's & SOC integration. Includes building and integrating any of the Debug IPs such as the ones provided by ARM Coresight. Proficiency in System Verilog & scripting along with excellent knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting). Good understanding in clock crossing techniques & UPF (Low power intent). Previous experience working on post-silicon debug / validation, especially during power ON & FA/FI. Hands on contribution towards Debug Architecture along with good knowledge of Industry standard standards. Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable. Confident problem solver who thrives under pressure to find new, creative solutions.

Responsibilities

Define the micro-architectural implementation specification for debug IPs and lead a team for IP and product deliverables. Work closely with validation engineers to enable silicon and refine debug execution methodologies.