Principal Design Verification Engineer at Marvell Technology

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

14 Mar, 26

Salary

0.0

Posted On

14 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, CPU Sub-Systems, Test Bench Development, Mentoring, SoC Verification, Digital Design Verification, ASIC Verification, SystemVerilog, UVM, Functional Coverage, Debug Skills, Verdi, Incisive, AMBA Protocols, GIT, C Language

Industry

Semiconductor Manufacturing

Description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M® product families. The SoC family of multi-core CPU processors and Custom SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications, whether they’re a major telecom organization or automotive company, etc. What You Can Expect Lead the design verification of complex CPU sub-systems and the full chip. Hands-on work on a test bench architecture, test bench development, test plan, and coverage plan is needed. Mentor and guide a team of design verification engineers. Own the subsystem verification flows, methodologies, and verification of IP/subsystem—conclude with the required verification criteria. What We're Looking For Bachelor’s degree in computer science, electrical engineering, or related fields and 12-15 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 10+ years of experience. Experience with processors and SOC architectures, such as interrupt controllers & Arm CPU sub-systems, is a must. Experience with SoC verification is a must. Experience with digital design verification at the SoC level. Proven track record in ASIC verification, from environment development to test development Candidates should have hands-on verification experience and proficiency using SystemVerilog and UVM. Should have experience in the constrained-random stimulus and use of functional coverage. Exposure to the C language is preferred. Strong debug skills and experience with debug tools such as Verdi and Incisive. Good knowledge of AMBA protocols—AXI, AHB, APB Creating a test bench, test plan, and coverage plan from scratch by hand on at least one complex project. Knowledge of the GIT version control system. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-CP1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Responsibilities

Lead the design verification of complex CPU sub-systems and the full chip. Mentor and guide a team of design verification engineers while owning the verification flows and methodologies.