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Principal Designer, Mask Design Engineering at Sandisk

Fujisawa, , Japan -

Full Time

Start Date

Immediate

Expiry Date

28 Apr, 26

Salary

0.0

Posted On

28 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

IC Layout, Layout Automation, Virtuoso Layout Editor, Calibre DRC, Synopsys LVS, Cross Team Collaboration

Industry

Semiconductor Manufacturing

Description

会社概要 Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. 求人内容 Key Responsibilities Layout for Peripheral circuit DRC/LVS Verification cross team collaboration with other site 資格 Your Experience 5+ years of experience in IC layout virtuoso layout editer Calibre DRC Synopsys LVS Nice to have English skills Knowledge of Layout automation Experienced management or leading Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: Mask Design Engineering Work Location: Ofuna Office--LOC_SNDK_Ofuna Office

Responsibilities

The principal designer will be responsible for layout for peripheral circuits and DRC/LVS verification. Collaboration with other teams across different sites is also a key aspect of the role.