Principal Digital Design Engineer at onsemi

Ireland, England, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

13 Sep, 26

Salary

0.0

Posted On

15 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Design Architecture, RTL Design, Low Power Design, ASIC Synthesis, Timing Analysis, System Verilog, Verilog, TCL, Perl, Python, Mixed Signal IC Design, CDC, UPF, Power Management ICs, FPGA, Emulation

Industry

Semiconductor Manufacturing

Description

*Description for Internal Candidates Responsibilities: onsemi is seeking a Principal Digital Design Dngineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Limerick, Ireland. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. Responsibilities for Internal Candidates In this role, you will focus on the following: * The candidate will lead the digital design architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding teams for the power management chips as well as executing various tool flows for IP quality control. * The candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies. * Drive architecture to micro-architecture to RTL implementation with the refining of features requirements throughout the design process. * Support the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA. * Knowledge of development of digital control peripherals, MCU systems. * Own technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces. * Identify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making. * Support post-silicon validation activities for your designs. * BS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments. * The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. * Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion). * Solid understanding of Verilog, TCL and Perl/Python/XML programming languages. * Experience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers. * Good understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages. * Understanding of digital architecture trade-offs for power, performance, and area. * Must have good written and verbal cross-functional communication skills. * BE/BTech in Electrical Engineering or related plus 10 years of experience, or MTech plus 8 years of experience. Qualifications for Internal Candidates * BS in Electrical Engineering or related plus 10 years of experience, or MS plus 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments. * The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. * Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion). * Solid understanding of Verilog, TCL and Perl/Python/XML programming languages. * Experience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers. * Good understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages. * Understanding of digital architecture trade-offs for power, performance, and area. * Must have good written and verbal cross-functional communication skills. * BE/BTech in Electrical Engineering or related plus 10 years of experience, or MTech plus 8 years of experience. Same Posting Description for Internal and External Candidates onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits [https://www.onsemi.com/careers/career-benefits] We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

Responsibilities

Lead the digital design architecture, RTL implementation, and synthesis for power management chips. Collaborate with global cross-functional teams to drive products from micro-architecture to post-silicon validation.