Principal Digital Design Engineer at Renesas Electronics

Duluth, Georgia, United States -

Full Time

Start Date

Immediate

Expiry Date

15 May, 26

Salary

0.0

Posted On

14 Feb, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Verilog, ASIC Design, FSM Design, Low Power Techniques, High-Speed Design, Synthesis, Static Timing Analysis, Logic Equivalence Checking, Formal Verification, Linting, CDC/RDC Checking, ECO Implementation, Design Constraints, Gate-Level Simulations, ATPG

Industry

Semiconductor Manufacturing

Description

Company Description Renesas is seeking a talented individual for their memory interface products team. These products primarily serve data centers for AI and cloud computing, delivering the highest bandwidth for intensive computing while consuming low power. This exciting role is responsible for the development of the digital sections of leading-edge memory data buffer chips for DDR5, DDR6, and beyond. Job Description Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set Apply clocking controls, FSM design, low power techniques, and high-speed design concepts Participate in design, architecture, and verification reviews Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking Create documentation targeting design, verification, and test teams Assist with the proposal, definition, documentation, and implementation of new features Mentor and train junior engineers and New College Grad engineers Qualifications Education: Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with minimum 12+ years of experience 8+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow Experience in architecting digital designs and writing device-level or sub-system specifications. Fluent in Verilog RTL coding and ASIC design methodology Expertise in digital design implementation, including logical synthesis and DFT insertion with high coverage Experience with static timing analysis and creation of place and route constraints Proficiency in formal verification, linting, and CDC/RDC checking Knowledge of asynchronous clock crossings and synthesis implications of RTL Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists Competence in developing design constraints for synthesis, STA, and P&R hand-off Experience with gate-level simulations and understanding the causes and implications of timing violations Familiarity with ATPG generation and ATE support (a plus) Experience in DFT or physical design (a plus) Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 22,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Shape Your Future with Us. Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement. Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas. We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Employment Type: Regular (PERM) Remote Work Available: No

Responsibilities

This role involves proposing, architecting, and designing RTL in Verilog for leading-edge memory data buffer chips used in DDR5, DDR6, and beyond, primarily serving data centers for AI and cloud computing. Responsibilities also include overseeing digital backend design processes like synthesis and static timing analysis, and mentoring junior engineers.