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Principal Engineer Analog Layout at Infineon Technologies AG Australia

Simpang Ampat, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

19 Feb, 26

Salary

0.0

Posted On

21 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog Layout, Layout Verification, Troubleshooting, VLSI, Submicron CMOS, Technical Skills, Analytical Skills, Problem-Solving Skills, Team Player, Interpersonal Skills, Communication Skills, Layout Productivity, Quality Improvement, Methodology Improvement, High Voltage Layout, Block/IP/Chip Floor Planning

Industry

Semiconductor Manufacturing

Description

Participate in block/IP/chip floor planning from scratch, performing routing & layout verification (such as LVS, DRC, Antenna & others) and troubleshooting the results Bachelor's Degree in Electrical/Electronic Engineering/Physics with VLSI exposure or equivalent 12 to 15 years of job experience in layout design field is preferred Hands on experience in analog layout from scratch Knowledge &experience in radio high voltage layout will be a plus Deep understanding of analog circuit layout concepts in submicron CMOS technologies Possess strong technical, analytical & problem-solving skills in layout design Capable in driving ideas towards implementation for layout productivity, quality and methodology improvement Ability to work as strong team player and participate in cross-functional activities Good interpersonal, verbal and communication skill with good initiative at work We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.

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Responsibilities

Participate in block/IP/chip floor planning from scratch and perform routing & layout verification. Troubleshoot results to ensure layout quality and productivity.