Principal Engineer, ASIC Development Engineering (Front End CAD -RTL Integr at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

16 Aug, 26

Salary

0.0

Posted On

18 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Integration, LINT Methodology, CDC Verification, RDC Verification, ECO Flows, PPA Estimation, TCL, Python, Perl, Shell Scripting, Synopsys SpyGlass, Cadence HAL, Siemens Questa AutoCheck, Cadence Conformal, Synopsys Fusion Compiler, Cadence Genus

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description About the Role SanDisk's ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. The Design Enablement team enables the Technology, Methodology, and Flows to ASIC design teams to deliver best-in-class products. As the Front End CAD/Methodology Engineer, you will play a pivotal role in developing and delivering robust RTL design methodologies on cutting-edge technology nodes, enabling best-in-class quality and productivity. This role is ideal for a seasoned front-end methodology leader who enjoys solving complex RTL integration challenges, working closely with design teams, and driving innovation across flows, tools, and automation. Key Responsibilities RTL Integration & Assembly: Develop and maintain robust RTL integration flows, including IP stitching, hierarchical assembly, and top-level SoC integration methodologies. LINT Methodology: Architect and maintain comprehensive RTL linting flows using industry-standard tools (e.g., Synopsys SpyGlass, Cadence HAL, Siemens Questa AutoCheck) to ensure coding style compliance, synthesizability, and design quality. CDC (Clock Domain Crossing) Verification: Define and enforce CDC verification methodologies, including: Structural CDC analysis Synchronizer verification Protocol checking and metastability analysis CDC coverage closure and signoff criteria RDC (Reset Domain Crossing) Verification: Own and evolve RDC verification flows to ensure proper reset synchronization, reset sequencing, and reset-related functional correctness. ECO (Engineering Change Order) Flows: Develop and support RTL and netlist ECO methodologies for late-stage design changes, ensuring minimal impact on timing, area, and verification closure. Early PPA Estimation: Implement and maintain early Power, Performance, and Area (PPA) estimation flows on RTL to enable architecture exploration and design trade-off analysis before synthesis. Flow Automation & Infrastructure: Develop scripts, automation frameworks, and regression infrastructure to improve flow robustness, repeatability, and productivity across multiple ASIC programs. Shift-Left Methodologies: Drive correct-by-construction and shift-left approaches to catch RTL issues early, reducing iteration cycles and accelerating design closure. Tool Qualification & Evaluation: Lead tool evaluation, qualification, and deployment for front-end CAD tools; work with EDA vendors to resolve issues and drive feature enhancements. Collaboration: Work closely with RTL designers, verification engineers, synthesis teams, and physical design teams to identify recurring issues and introduce automation, checks, and best practices. Qualifications Experience: ~10 years of experience in front-end ASIC design, RTL integration, CAD, or methodology roles. RTL Design Understanding: Strong understanding of RTL design principles, including coding styles, synthesizability, design hierarchy, and design-for-verification best practices. LINT Expertise: Hands-on experience with RTL linting tools and methodologies, with a deep appreciation of coding quality and its impact on downstream flows (synthesis, timing, verification). CDC/RDC Verification: Expertise in clock and reset domain crossing verification and signoff, including: CDC structural analysis and protocol verification RDC analysis and reset synchronization checks Metastability and synchronizer verification Waiver management and signoff closure ECO Flows: Proven experience with RTL and gate-level ECO methodologies for late-stage design changes. Early PPA Estimation: Experience with early Power, Performance, and Area (PPA) estimation tools and flows at the RTL level. Flow Development: Demonstrated ability to architect, develop, and deploy end-to-end front-end CAD flows for multi-million gate SoC designs. Tool Proficiency: Strong working knowledge of industry-standard front-end tools such as: Industry Standard RTL Quality check tools(LINT, CDC, RDC) Cadence Conformal / Other Functional Eco Tools Synopsys Fusion Compiler/Cadence Genus (for PPA estimation) Other Early PPA estimation EDA tools Scripting & Automation: Proficiency in scripting and automation using TCL, Python, Perl, and/or Shell scripting. Education: B.Tech / M.Tech / MS in VLSI Design, Electrical Engineering, Computer Engineering, or a related field (or equivalent industry experience). Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

Develop and maintain robust RTL integration, linting, and clock/reset domain crossing verification methodologies for high-scale memory controllers. Drive flow automation, early PPA estimation, and shift-left approaches to accelerate ASIC design closure.