Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design) at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

27 Apr, 26

Salary

0.0

Posted On

27 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

High-Speed I/O Design, TX/RX Design, DDR4, DDR5, HBM, Timing Budget Analysis, IO Standards, ESD Circuit Design, Cadence Virtuoso, Synopsys Custom Compiler, SPICE Simulators, CMOS Technologies, FinFET Nodes, Statistical Simulation, Design Methodologies, Technical Guidance

Industry

Semiconductor Manufacturing

Description

Company Description SanDisk Corporation is a global leader in flash storage technology, offering a comprehensive portfolio that spans consumer, client, and enterprise solutions. Trusted by many of the world’s most prominent organizations, SanDisk’s products are deployed extensively across diverse environments, enabling reliable data storage, seamless access, and significant value creation from the information they manage. Job Description Principal Engineer will contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes. Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers. Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule. Collaborate with layout engineers by providing clear guidance, performing schematic‑layout reviews, and ensuring design robustness and layout quality. Support SOC integration activities, debug integration issues, and participate in post‑tapeout efforts including silicon characterization and performance validation. Provide technical guidance to junior engineers, support their ramp‑up, and contribute to fostering a culture of technical excellence. Contribute ideas for design improvements, propose enhancements to design methodologies, and support the development of efficient flows and best practices. Qualifications Bachelor’s or Master’s degree in Electronics & Telecommunication or Electrical Engineering. 9+ years of hands-on experience in High‑Speed I/O design. Strong hands-on experience in TX/RX design for high-speed memory interfaces such as DDR4, DDR5, and HBM, including comprehensive timing budget analysis. Practical experience with IO standards and IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration circuits, HV‑tolerant and fail‑safe IOs, and crystal oscillators. Expertise in ESD circuit design, including familiarity with ESD guidelines, methodologies, and best practices across multiple process nodes. Proficient with industry‑standard custom design tools such as Cadence Virtuoso, Synopsys Custom Compiler, and SPICE simulators (HSPICE, Spectre, FineSim), including statistical simulation methodologies. Exposure to creating EDA models such as Verilog models, Liberty (.lib) files, etc., is beneficial. Deep understanding of CMOS technologies, including FinFET nodes and awareness of associated DSM (Deep Sub‑Micron) challenges. Highly analytical mindset with the ability to work effectively in multidisciplinary teams. Creative, innovative thinker with strong personal ownership and attention to detail. Strong theoretical foundation complemented by a pragmatic, solution‑oriented approach. Excellent verbal and written communication skills with experience collaborating across global teams. Strong documentation and presentation skills. Additional Information All your information will be kept confidential according to EEO guidelines. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The Principal Engineer will design and develop IO and high-speed interface solutions for next-generation SoCs. Responsibilities include evaluating design approaches, collaborating with layout engineers, and supporting SOC integration activities.