Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design) at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

10 Jul, 26

Salary

0.0

Posted On

11 Apr, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC design, High-speed I/O design, TX/RX design, DDR4, DDR5, HBM, Timing budget analysis, ESD circuit design, Cadence Virtuoso, Synopsys Custom Compiler, SPICE simulators, FinFET, RTL design, PVT calibration, Silicon characterization, Circuit design

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Principal Engineer will contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes. Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers. Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule. Collaborate with layout engineers by providing clear guidance, performing schematic‑layout reviews, and ensuring design robustness and layout quality. Support SOC integration activities, debug integration issues, and participate in post‑tapeout efforts including silicon characterization and performance validation. Provide technical guidance to junior engineers, support their ramp‑up, and contribute to fostering a culture of technical excellence. Contribute ideas for design improvements, propose enhancements to design methodologies, and support the development of efficient flows and best practices. Qualifications Bachelor’s or Master’s degree in Electronics & Telecommunication or Electrical Engineering. 9+ years of hands-on experience in High‑Speed I/O design. Strong hands-on experience in TX/RX design for high-speed memory interfaces such as DDR4, DDR5, and HBM, including comprehensive timing budget analysis. Practical experience with IO standards and IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration circuits, HV‑tolerant and fail‑safe IOs, and crystal oscillators. Expertise in ESD circuit design, including familiarity with ESD guidelines, methodologies, and best practices across multiple process nodes. Proficient with industry‑standard custom design tools such as Cadence Virtuoso, Synopsys Custom Compiler, and SPICE simulators (HSPICE, Spectre, FineSim), including statistical simulation methodologies. Exposure to creating EDA models such as Verilog models, Liberty (.lib) files, etc., is beneficial. Deep understanding of CMOS technologies, including FinFET nodes and awareness of associated DSM (Deep Sub‑Micron) challenges. Highly analytical mindset with the ability to work effectively in multidisciplinary teams. Creative, innovative thinker with strong personal ownership and attention to detail. Strong theoretical foundation complemented by a pragmatic, solution‑oriented approach. Excellent verbal and written communication skills with experience collaborating across global teams. Strong documentation and presentation skills. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The Principal Engineer will design and develop IO and high-speed interface solutions for next-generation SoCs in advanced CMOS technology nodes. They will also collaborate with layout engineers, support SOC integration, and provide technical guidance to junior team members.