Principal Engineer, ASIC Development Engineering (Physical Design, PNR, flo at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

03 Sep, 26

Salary

0.0

Posted On

05 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, PnR, Floorplanning, Timing Closure, Clock Tree Analysis, Low-power Design, Synopsys Fusion Compiler, Cadence Innovus, ASIC Development, Digital Design Fundamentals, IP Integration, DFT Collaboration, Semiconductor Fabrication, Design Analysis, Problem Solving, Technical Documentation

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance, and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Position Overview: We are seeking a highly skilled and experienced Principal Engineer for our PNR function. The successful candidate will be part to a team of talented engineers responsible for ensuring the PNR convergence of our complex semiconductor designs. This role requires a deep understanding of PNR methodologies, leadership skills, and a strategic vision to drive continuous improvement in our PNR processes. Key Responsibilities: Own subsystem/block-level floorplanning and end-to-end place-and-route (PnR) flow for low-power, high-performance designs, including debugging of timing, power, and area issues, clock tree analysis, and contributing to full-chip timing convergence and closure. Collaborate closely with cross-functional teams, including Design and DFT, to streamline and enhance the PnR flow. Drive robust IP integration strategies to ensure high-quality ASIC delivery while minimizing schedule risks. Perform in-depth design and timing analysis to identify critical paths and implement effective strategies to mitigate timing violations and improve overall design convergence. Stay current with industry trends and emerging technologies in PnR and related domains, and incorporate best practices into team workflows. Prepare and present comprehensive technical analyses, reports, and documentation to stakeholders. Promote a culture of innovation, collaboration, and continuous improvement within the PnR team. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. Minimum of 8 years of experience in the Place and Route (PnR) domain. Demonstrated track record of successful PnR execution across projects. Strong expertise in industry-standard PnR tools and methodologies (e.g., Synopsys Fusion Compiler, Cadence Innovus). Solid understanding of digital design fundamentals, physical design concepts, and semiconductor fabrication processes. Strong analytical and problem-solving capabilities, with a strategic mindset. Excellent communication and interpersonal skills, with the ability to collaborate effectively across cross-functional teams and stakeholders. Proven ability to prioritize tasks and manage multiple projects concurrently. Proactive, results-driven mindset with a strong focus on innovation and continuous improvement. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Location (Secondary): Hyderabad Office--LOC_SNDK_Hyderabad Office Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The role involves owning subsystem floorplanning and end-to-end place-and-route flows for high-performance, low-power ASIC designs. The engineer will drive timing convergence, IP integration, and collaborate with cross-functional teams to optimize PnR processes.