Principal Engineer, ASIC Development Engineering (Physical verification Eng at Sandisk

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

02 Jul, 26

Salary

0.0

Posted On

03 Apr, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical verification, Calibre, DRC, LVS, ESD, ERC, ANT, Multi voltage domain, TSMC 5nm, Cadence Innovus, FC, Virtuoso, Power gating, ASIC development, Physical design, Tapeouts

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description JOB Description : Take the leadership role of executing and signing off physical verification for block and full chip. Strong fundamentals in physical design verification using Calibre tool. Strong experience in multi voltage domain and design experience with multi-million instances. Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeouts Experience of working in lower tech nodes (TSMC5nm and below) Familiarity of PnR flows and tools such as Cadence Innovus/FC is must. Knowledge and hands on virtuoso experience is plus. Experience in power gating digital designs is a plus. Excellent verbal and written communication skills are required. Perform block and full-chip physical verification and work with the physical design team to close design issues Experience level : Minimum 8 to 12 years Qualifications Bachelor’s/Masters’ degree in Electronics and communication, Electronics and Electrical engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Hyderabad Office--LOC_SNDK_Hyderabad Office

Responsibilities

The candidate will lead the execution and sign-off of physical verification for block and full-chip designs. They will collaborate with the physical design team to resolve DRC, LVS, ESD, ERC, and ANT violations to ensure successful tapeouts.