Principal Engineer, ASIC Development Engineering (RTL Design) at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

21 Apr, 26

Salary

0.0

Posted On

21 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SoC Architecture, RTL Design, Verilog, SystemVerilog, Digital Design, Synthesis, Static Timing Analysis, DFT Concepts, EDA Tools, Cross-Functional Collaboration, Mentorship, Technical Leadership, Design Optimization, High-Speed Interfaces, Low-Power Design Techniques, Scripting Languages

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description About the Role: We are seeking a highly experienced and motivated Principal Engineer specialising in SoC RTL Design for System-on-Chip (SoC) solutions. As a key technical skill, you will drive the SoC Architecture, Design, and integration of complex digital systems, collaborating with cross-functional teams to deliver next-generation semiconductor products. Key Responsibilities: Define and review SoC architecture and design specifications. Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog. Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power. Contribute to IP selection, evaluation, and integration in SoC designs. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels. Qualifications Required Skills & Experience Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field. 9+ years of experience in digital design, with a focus on RTL design for complex SoCs. Deep expertise in Verilog/SystemVerilog. Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug. Experience with synthesis, static timing analysis, and DFT concepts. Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification). Proven track record of leading technical teams and delivering successful silicon. Excellent analytical, problem-solving, and communication skills. Passion for innovation and delivering high-quality, scalable solutions. Preferred Expertise: Experience with high-speed interfaces (PCIe, LPDDR5, High Speed Memories etc.). Expertise in low-power design techniques and high-speed interfaces. Familiarity with scripting languages (Perl, Python, TCL) for design automation. Participation in silicon bring-up and post-silicon validation Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The Principal Engineer will define and review SoC architecture and design specifications, develop high-quality RTL, and ensure robust design methodologies. They will also drive cross-functional collaboration and provide technical leadership to engineering teams.