Principal Engineer, Design Rule & Design Enablement Lead at Micron Technology

Tlaquepaque, jalisco, Mexico -

Full Time

Start Date

Immediate

Expiry Date

16 Mar, 26

Salary

0.0

Posted On

16 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Rules, Test Structures, Process Integration, Yield Enhancement, Product Engineering, Layout Efficiency, Manufacturability, DRAM Process Flow, Sense Amp, Word-line Driver, Anti-Fuse, CAD Interactions, Data Post-processing, Design Rule Checks, Problem Resolution, Communication

Industry

Semiconductor Manufacturing

Description

Lead efforts to develop and refine Design Rules, Requirements, and Test Structures for all DRAM generations. Manage test structure evaluation to support next-gen device development and quantify process margins. Define sub-milestones within layout schedules and ensure timely execution across teams. Address process window vs. die size issues arising from database layout techniques. Collaborate with Design, Product Engineering, Process Integration, Business Units, and Quality teams to optimize PPAC (Performance, Power, Area, Cost). Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations. Strategically partner with teams to resolve process issues related to layout and prioritize solutions. Document and communicate complex problem resolutions and drive cross-node design rule alignment. Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams. Improve documentation of R&D activities for design rule improvement Ability to define and implement design rules within APR workflows to enhance layout efficiency and manufacturability. BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field Senior level (5+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desired Experience with Test Structure Design and characterization Success in resolving sophisticated issues Think and communicate clearly in urgent and stressful situations Possess a deep understanding of the DRAM process flow, as well as the function and purpose of major DRAM components, such as Sense Amp, Word-line driver, and Anti-Fuse Exposure and familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle

Responsibilities

Lead the development and refinement of Design Rules and Test Structures for DRAM generations. Collaborate with various teams to optimize performance, power, area, and cost while ensuring timely execution of layout schedules.