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Principal Engineer, Design Rule & Design Enablement Lead at Micron Technology
Tlaquepaque, jalisco, Mexico -
Full Time

Start Date

Immediate

Expiry Date

23 Jan, 26

Salary

0.0

Posted On

25 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Design Rules, Test Structures, Process Margins, Layout Schedules, Process Window, Database Layout Techniques, PPAC Optimization, Design Rule Checks, Problem Resolution, Cross-node Design Rule Alignment, Documentation, APR Workflows, Layout Efficiency, Manufacturability

Industry

Semiconductor Manufacturing

Description
Lead efforts to develop and refine Design Rules, Requirements, and Test Structures for all DRAM generations. Manage test structure evaluation to support next-gen device development and quantify process margins. Define sub-milestones within layout schedules and ensure timely execution across teams. Address process window vs. die size issues arising from database layout techniques. Collaborate with Design, Product Engineering, Process Integration, Business Units, and Quality teams to optimize PPAC (Performance, Power, Area, Cost). Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations. Strategically partner with teams to resolve process issues related to layout and prioritize solutions. Document and communicate complex problem resolutions and drive cross-node design rule alignment. Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams. Improve documentation of R&D activities for design rule improvement Ability to define and implement design rules within APR workflows to enhance layout efficiency and manufacturability.
Responsibilities
Lead the development and refinement of Design Rules and Test Structures for DRAM generations. Collaborate with various teams to optimize performance, power, area, and cost while ensuring robust design rule checks.