Principal Engineer, Firmware Engineering- low-level firmware, PCIe at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

29 Dec, 25

Salary

0.0

Posted On

30 Sep, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Firmware Development, System Software Development, C/C++ Programming, Kernel Scheduling, Data Orchestration, PCIe, Memory Management, DMA Engines, Embedded Systems, Performance Tuning, Debugging, Cross-Functional Collaboration, Mentorship, Deep Learning Frameworks, Technical Leadership, Analytical Skills

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We're looking for a highly accomplished and visionary Principal Engineer to lead the development of our NPU firmware runtime for the Next Gen Computational Flash Controller project. You'll be the technical owner of the device-side software stack that orchestrates all NPU operations. This is a rare opportunity to define the architecture of a high-performance compute platform, from kernel scheduling to data orchestration, at the deepest levels of the system. Key Responsibilities 🛠️ Architectural Leadership: Serve as the technical lead for the entire NPU firmware runtime. You'll define the architecture for the communication and control plane that interacts with the host-side software stack via the PCIe driver. Kernel Orchestration: Design and implement the firmware for loading, scheduling, and executing kernels on the NPU. You will optimize the entire workflow from host command receipt to kernel launch, ensuring minimal latency and maximum throughput. Data Flow and DMA Engine: Architect the firmware responsible for managing high-bandwidth data flow. This includes interfacing with the SRAM to stage data and orchestrating the DMA engine to move data efficiently between the host, DRAM, and High-Bandwidth Flash (HBF). Performance Tuning: Profile, analyze, and optimize the end-to-end performance of the NPU runtime. You'll identify bottlenecks at the firmware, hardware, and driver layers, and propose innovative solutions. Cross-Functional Collaboration: Work closely with the host-side software teams (PyTorch), hardware design teams, and silicon engineers to define APIs, debug complex issues, and ensure a seamless, high-performance solution. Mentorship: Act as a mentor and technical guide to other firmware and software engineers, fostering a culture of technical excellence and innovation Qualifications Experience: 7+ years of hands-on experience in low-level firmware or system software development. Architectural Acumen: Proven experience in defining the architecture of complex embedded or device-side systems. Technical Expertise: Mastery of C/C++ with a focus on writing high-performance, concurrent, and real-time code. Deep understanding of system architecture, including PCIe, memory management, and DMA engines. Experience with hardware bring-up, embedded processors, and on-chip peripherals. Knowledge of deep learning frameworks (e.g., PyTorch) and the underlying computation graphs. Leadership Skills: Demonstrated ability to lead complex technical projects and influence a diverse group of stakeholders without direct authority. Problem-Solving: Exceptional debugging and analytical skills, with a track record of solving the most challenging system-level problems. Education: Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Responsibilities

Lead the development of NPU firmware runtime for the Next Gen Computational Flash Controller project. Define the architecture of a high-performance compute platform and optimize the firmware for kernel orchestration and data flow management.