Principal Engineer – Memory Training Architecture at Advanced Micro Devices, Inc

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

19 Jul, 26

Salary

0.0

Posted On

20 Apr, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Memory Training Architecture, DDR5, LPDDR5, LPDDR6, RTL Design, SystemVerilog, Calibration Algorithms, Post-silicon Bring-up, Firmware Development, Memory Controller, PHY Interaction, Signal Integrity, Power Integrity, C Programming, Validation, Technical Leadership

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Principal Engineer – Memory Training Architecture The Role As a Principal Engineer in the Memory Training Development team, you will provide architectural leadership and deep technical ownership for next‑generation memory training solutions across DDR5, LPDDR5, and LPDDR6. You will shape long‑term technical direction, define robust architectures, and drive innovation in high‑speed memory training algorithms that enable high‑quality silicon products. This role emphasizes enduring technical impact—influencing designs across multiple generations, guiding critical trade‑offs, and ensuring execution excellence—without people management as a primary responsibility. The Person You are a recognized technical authority who consistently solves complex, ambiguous problems and elevates engineering quality across organizations. You influence through technical depth, judgment, and collaboration, and are equally effective operating at architectural, algorithmic, and hands‑on implementation levels. You are comfortable owning high‑risk technical decisions, working across organizational boundaries, and driving clarity in uncertain problem spaces. Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions—including RTL logic, firmware routines, and algorithmic flows—into AMD’s system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements Key Responsibilities Act as a principal technical authority for memory training architecture and development Define and evolve end‑to‑end memory training architectures and specifications for DDR5, LPDDR5, and LPDDR6 Drive innovation in high‑speed memory training algorithms, robustness, and convergence strategies Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines Provide architectural guidance and technical leadership across Circuit Design, Architecture, Logic Design, Design Verification, and Post‑Silicon teams globally Influence design quality through architecture reviews, deep technical mentorship, and principled trade‑off decisions Lead and support post‑silicon bring‑up, validation, characterization, optimization, and product readiness efforts Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces Clearly articulate complex technical concepts to senior technical peers, architects, and leadership Preferred Experience Proven record of sustained, high‑impact contributions to memory training architecture and silicon delivery Experience owning or shaping architectural direction across multiple product generations Deep understanding of DDR memory systems and controller/PHY interactions (DDR5, LPDDR5, LPDDR6) Been exposed to memory controller and PHYs from different IP vendors Hands‑on experience with post‑silicon bring‑up and lab‑based validation Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of silicon packaging and PCB design, with awareness of signal and power integrity Demonstrated ability to make sound technical decisions in complex, high‑risk design spaces Strong influence skills without formal authority; effective cross‑organizational collaborator Working knowledge of C; embedded experience a plus Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player Academic Credentials Advanced degree in Electrical Engineering or related field preferred, or equivalent professional experience. Typically 15+ years of experience in logic design, including significant depth in memory training. #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The Principal Engineer will provide architectural leadership for next-generation memory training solutions, defining specifications and driving innovation in high-speed memory training algorithms. They will collaborate with cross-functional teams to integrate calibration solutions and lead post-silicon bring-up and validation efforts.