Principal Engineer – Physical Design at Microchip Technology Inc.

, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

18 Aug, 26

Salary

0.0

Posted On

20 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Floorplanning, P&R Tools, Timing Closure, Low Power Design, Static Timing Analysis, Physical Verification, TCL, Perl, Shell Scripting, Verilog, VHDL, UNIX/LINUX, ASIC Development, DFM, LEC

Industry

Semiconductor Manufacturing

Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, connectivity, and power management semiconductors. Its easy-to-use development tools and comprehensive product portfolio enable customers to create optimal designs while reducing total system cost, risk, and time to market. The company's solutions serve more than 130,000 customers across the industrial, automotive, consumer, aerospace and defense, communications and computing markets. The corporate CAD and ES (Engineering Services) group offers industry leading digital and mixed-signal design implementation of full RTL2GDS spectrum on advanced technology nodes with cutting edge EDA tooling platform. As a Principal Physical Design engineer, the candidate will be supervised by a local manager, engaging into projects to perform layout floorplanning all the way to GDS convergence and ensure the design is implemented correctly with various checks/verification/audit. He/she will be involved and drive design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology. Responsibilities: Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices. Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope. Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows. Perform and debug LEC in ensuring design equivalence against synthesized gate-level netlist. Guiding/leading junior members of the team with effective coaching approach. Enhance tools, flows and methodologies to meet design TAT Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule Requirements/Qualifications: Qualifications: This position requires at least BSEE with 6-10 years of ASIC development experience in a fast paced environment. You are required to have expertise in a wide range of areas in design, tools and flows: BEng/MEng in EE or equivalent with the completion of several complexes ASIC or IC tapeouts in VDSM process technology nodes. Experience taking large blocks to timing, physical design and DRC/LVS closure. Experience in physical design with the understanding of VDSM effects and issues with excellent debugging and analytical skills. Understand floor planning, placement and optimization for timing closure, clock network planning, power distribution planning and routing. Experienced in main P&R tools such as Synopsys ICC/PT, Cadence Innovus and ETS. Post layout physical verification and DFM rules (Cadence PVS). Understand Low Power methodology, Static Timing Analysis, Signal/Power Integrity to meet design goals. Experienced in scripting (TCL, PERL & Shell) and working knowledge of HDL (Verilog, VHDL) with solid understanding of UNIX/LINUX. Knowledge of synthesis tools (e.g. Design compiler, Genus or equivalent) and static timing analysis tools (e.g. Prime Time or equivalent) is a plus. Excellent verbal and written communication skills. Strong interpersonal skills. Ability to lead and mentor others and work under challenging environment Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes. At Microchip, employees are our greatest strength. As one of the top performing semiconductor companies in the world, we are led by a set of guiding values and a mission to empower innovation to enhance the human experience. We work tirelessly to create a company culture that highlights how important every employee is to our mission. Microchip Recruitment Privacy Notice Recruitment Scam Alert Microchip will never: Request banking or payment information during the application or interview process. Ask candidates to register or pay for a training class as part of the application or interview process. Ask candidates to receive or ship packages or goods as part of the recruitment process. Use email address not ending with "@microchip.com". Use instant messaging to communicate. Be wary of generic emails or vague job details. If something feels suspicious, stop communicating immediately. To report potential scams, contact us at HR.Compliance@microchip.com.

Responsibilities

Lead the physical design process from floorplanning to GDS convergence, ensuring optimal PPA metrics and design correctness. Drive the development of best-in-class design flows and methodologies while mentoring junior team members.