Principal Engineer, RTL Design at Sandisk

Zhubei City, , Taiwan -

Full Time

Start Date

Immediate

Expiry Date

28 Jan, 26

Salary

0.0

Posted On

30 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, ASIC Design, Verilog, System Verilog, Digital Design Flow, AI Tools, GitHub Copilot, Problem Solving, Communication, Teamwork, Low-Power Design, High-Speed Interfaces, Python, TCL, Mentorship, Collaboration

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Are you ready to push the boundaries of what's possible in technology? Join the trailblazers at Sandisk. As a Principal Engineer you will be at the forefront of designing high-performance SoCs for storage solutions. By leveraging your expertise in RTL design and modern tools like GitHub Copilot, you will enhance the design process and productivity. You will collaborate with cross-functional teams to deliver groundbreaking solutions that meet our high standards of quality and performance. Key Responsibilities: Innovate, implement, and verify RTL code for complex ASICs. Performed design tasks across various design stages. Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process. Collaborate with hardware and software teams for seamless integration. Provide mentorship to junior engineers. Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design. Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. Hands-on experience in digital IP/SoC design: minimum 7 years with a Bachelor's degree, or 6 years with a Master’s degree. Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog. Familiarity with the whole digital design flow. Proficiency in leveraging AI tools, including GitHub Copilot, for design and development. Strong problem-solving skills and the ability to thrive in a dynamic environment. Excellent communication and teamwork abilities. Preferred Qualifications: Experience in low-power design techniques and methodologies. Familiarity with high-speed interfaces (e.g., SD Express, Compact Flash, PCIe, DDR). Proficiency in scripting languages (e.g., Python, TCL) for automation Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Responsibilities

Innovate, implement, and verify RTL code for complex ASICs while collaborating with cross-functional teams. Utilize advanced AI-driven tools to streamline the design process and provide mentorship to junior engineers.