Principal Engineer - Verification / AMS / SerDes at Marvell Technology

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

07 Sep, 26

Salary

0.0

Posted On

09 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, UVM, SerDes Verification, AMS Verification, Mixed-Signal Verification, Gate-Level Simulation, Power-Aware Verification, CDC/RDC Validation, PCIe, Ethernet, PAM4/PAM2, Register Modeling, VIP Integration, Silicon Bring-up, Verification Architecture, Technical Leadership

Industry

Semiconductor Manufacturing

Description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Central Engineering AMS‑IP delivers high‑quality analog and mixed‑signal IP and verification for Marvell’s advanced IPs, SoCs and platforms. The team provides scalable, reusable solutions across high‑speed interfaces (SerDes, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first‑time‑right silicon, reduced integration risk, and faster time‑to‑market through strong design‑verification convergence and system‑level validation. What You Can Expect Role Summary The Principal Engineer will provide technical and methodological leadership across complex high‑speed SerDes, AMS, and Central Engineering verification programs. This role requires deep hands‑on expertise combined with the ability to define verification strategy, influence architecture, mentor senior engineers, and drive execution excellence across multiple projects and nodes. Key Responsibilities • Own end‑to‑end verification strategy and execution for complex SerDes / AMS / mixed‑signal IPs across multiple process nodes (e.g., 5nm, 3nm, 2nm). • Define and drive verification architecture spanning digital, AMS, firmware‑assisted, and system‑level verification. • Lead design‑verification convergence, influencing architecture, register definition, calibration flows, and feature feasibility. • Drive resolution of complex cross‑domain issues involving RTL, AMS, firmware, VIPs, and silicon behaviors. • Serve as the technical authority and escalation point for hard verification, coverage, debug, and sign‑off challenges. • Lead Gate‑Level Simulation (GLS) strategy, power‑aware verification, CDC/RDC validation, and post‑silicon correlation. • Define verification approaches for new features. • Mentor juniors, raising the bar on technical rigor, ownership, and execution discipline. • Drive methodology, tooling, and productivity improvements, including automation and AI‑assisted verification where applicable. • Proactively identify technical and schedule risks and drive early mitigation across teams. What We're Looking For Required Technical Qualifications • 14+ years of strong hands‑on experience in verification of IP / AMS systems. • Deep expertise in one or more areas: • High‑speed SerDes (PCIe, Ethernet, D2D, PAM4/PAM2) • AMS / Mixed‑Signal verification • Register modeling, firmware‑driven flows • Strong proficiency in SystemVerilog, UVM, and advanced verification methodologies. • Experience with protocol/VIP integration (Synopsys, Cadence, Mentor, Avery, etc.). • Hands‑on experience with GLS, power‑aware verification, timing‑aware flows, and silicon bring‑up support. • Ability to analyze and debug issues spanning pre‑silicon to post‑silicon correlation. • Strong understanding of system‑level behavior, not just block‑level verification. Leadership & Behavioral Expectations • Acts as a technical multiplier, enabling success across multiple teams and projects. • Leads through influence, credibility, and ownership, not hierarchy. • Makes sound trade‑offs under ambiguity, balancing quality, schedule, and risk. • Communicates complex technical issues with clarity and structure to diverse audiences. • Models engineering excellence, integrity, and accountability. • Invests in developing others, scaling impact beyond personal execution. Nice‑to‑Have / Differentiators • Experience defining verification frameworks reused across IPs / programs. • Innovation in AI‑assisted verification, automation, or coverage optimization. • Publications, patents, or conference presentations (DVCon, VLSI‑D, internal forums). • Experience working across globally distributed teams and central engineering models. Success Criteria • Raises the technical bar and predictability of SerDes/AMS verification. • Enables teams to execute faster without compromising quality. • Becomes a trusted technical voice for architecture, verification strategy, and leadership. • Leaves behind scalable frameworks, stronger engineers, and durable methodologies. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Responsibilities

Lead the end-to-end verification strategy and execution for complex high-speed SerDes and AMS IPs across advanced process nodes. Drive design-verification convergence and mentor senior engineers to ensure first-time-right silicon.