Start Date
Immediate
Expiry Date
20 Dec, 26
Salary
90000.0
Posted On
21 Sep, 26
Experience
12 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
Industry
Information Technology & Services
Date posted 09/17/2026
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
Firmware at the boundary between hardware and software is where you have built your career. A single miscalculation can mean the difference between a memory interface that trains cleanly and one that fails in the field, and that reality has shaped how you work. Performance is not just about writing tight code. It is about understanding what the silicon is actually doing when your code runs at boot time.
Dropping into RTL waveforms to debug firmware comes naturally to you. So does stepping back to question whether the algorithm itself needs rethinking. Profiling compiled code to find microcode level bottlenecks is the kind of work that keeps you engaged. The hardware is real, the constraints are real, and the problems do not solve themselves with abstractions.
Mentoring others matters to you, but so does staying curious about how new modeling techniques might change what is possible.
At Synopsys, the memory interface PHYs you work on will power the next generation of DDR, LPDDR, and HBM solutions.
What You'll Be Doing
The Impact You Will Have
What You'll Need
Who You Are
The Team You'll Be Part Of
You will be part of the Synopsys IP Group firmware development team based in Ottawa, focused on developing interface IP solutions for DDR, LPDDR, and HBM memory interfaces. The team works on the challenging problem of PHY-to-memory interface training for next-generation protocols and bus speeds, balancing runtime performance with quality of results. This is a team that values fresh perspectives and is committed to mentoring and integrating new members. You will have access to an advanced hardware lab with a library of testchips for real-world validation and optimization work.
Rewards and Benefits
How To Apply:
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Date posted 09/17/2026
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
Firmware at the boundary between hardware and software is where you have built your career. A single miscalculation can mean the difference between a memory interface that trains cleanly and one that fails in the field, and that reality has shaped how you work. Performance is not just about writing tight code. It is about understanding what the silicon is actually doing when your code runs at boot time.
Dropping into RTL waveforms to debug firmware comes naturally to you. So does stepping back to question whether the algorithm itself needs rethinking. Profiling compiled code to find microcode level bottlenecks is the kind of work that keeps you engaged. The hardware is real, the constraints are real, and the problems do not solve themselves with abstractions.
Mentoring others matters to you, but so does staying curious about how new modeling techniques might change what is possible.
At Synopsys, the memory interface PHYs you work on will power the next generation of DDR, LPDDR, and HBM solutions.
What You'll Be Doing
The Impact You Will Have
What You'll Need
Who You Are
The Team You'll Be Part Of
You will be part of the Synopsys IP Group firmware development team based in Ottawa, focused on developing interface IP solutions for DDR, LPDDR, and HBM memory interfaces. The team works on the challenging problem of PHY-to-memory interface training for next-generation protocols and bus speeds, balancing runtime performance with quality of results. This is a team that values fresh perspectives and is committed to mentoring and integrating new members. You will have access to an advanced hardware lab with a library of testchips for real-world validation and optimization work.
Rewards and Benefits
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